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| motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee r egarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specif ically disclaims any and all liability, including without limitation consequential or incidental damages. typical parameters which may be provided in motorola data sheets and/or speci fications can and do vary in different applications and actual performance may vary over time. all operating parameters, including typicals must be validated for each custom er application by customers technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intende d, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other applica tion in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such uninte nded or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against al l claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unautho rized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/affirmative action employer. document number 9s12c128dgv1/d 1 ?motorola, inc., 2002 mc9s12c family device user guide v01.05 covers also mc9s12gc family original release date: 25 jan 2003 revised: 11 february 2004 motorola, inc.
device user guide 9s12c128dgv1/d v01.05 2 revision history version number revision date effective date author description of changes 00.01 25.jan.03 25.jan.03 original version. based on c32 user guide version 01.12 00.02 07.feb.03 07.feb.03 enhanced portk description part number table revision in preface 00.03 25.feb.03 25.feb.03 qfp112 emulation pinout correction enhanced part number explanation in preface reduced pseudo stop current spec. for c64,c96,c128 00.04 15.apr.03 15.apr03 enhanced portad signal description corrected vddr description in 2.4.2 revised pin leakage in electrical parameters 00.05 05.may.03 05.may.03 spi timing parameter table correction output drive high value reduced in 3v range pe[4:2] pull-up spec out of reset changed 3v expansion bus timing parameters not tested in production minimum bus frequency speci?cation increased to 0.25mhz. 00.06 21.may.03 21.may.03 parameter classi?cation added to appendix table c-2. ioh changed to 4ma for 3v range. 01.00 15.jul.03 15.jul03 lvr level de?ned.for c32. run idd changed for c32. block guide reference table updated added pcb layout guide for pierce oscillator con?guration iol parameter updated in 3.3v range 01.01 12.aug.03 12.aug.03 updated partid listing due to c128 eco revision 01.02 20.nov.03 20.nov.03 changed doc number and cpu doc reference number included separate c32 lvi levels changed portm pull up reset state to enabled. 01.03 27.nov.03 27.nov.03 added references to the can-less gc-family no major revision number increment, since silicon functionality is not changed. added vddx connection in pcb layout ?gures 8-1.to 8-6 added part id for 2l45j mask set to part id table 01.04 27.jan.04 27.jan.04 table a-4 vdd/vddpll min when supplied externally now 2.35v reference s12fts128k1 in preface (was s12fts128k) reference to cpu guide corrected to version2 01.05 11.feb.04 11.feb.04 corrected ?ash sector sizes for c-family devices with >64k flash corrected preface table 0-1 16k part listing to gc16 without can added ppage speci?cations to memory map diagrams added ?ash timing parameters for 1024 byte sector size device user guide 9s12c128dgv1/d v01.05 3 table of contents section 1 introduction 1.1 overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3 1.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3 1.3 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 1.4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 1.5 device memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 1.6 detailed register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 1.7 part id assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 section 2 signal description 2.1 device pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 2.2 signal properties summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 2.2.1 pin initialization for 48 & 52 pin lqfp bond-out versions . . . . . . . . . . . . . . . . . . 56 2.3 detailed signal descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 2.3.1 extal, xtal oscillator pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 2.3.2 reset external reset pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 2.3.3 test / vpp test pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 2.3.4 xfc pll loop filter pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 2.3.5 bkgd / taghi / modc background debug, tag high & mode pin . . . . . . . 58 2.3.6 pa[7:0] / addr[15:8] / data[15:8] port a i/o pins . . . . . . . . . . . . . . . . . . . . 58 2.3.7 pb[7:0] / addr[7:0] / data[7:0] port b i/o pins . . . . . . . . . . . . . . . . . . . . . . 58 2.3.8 pe7 / noacc / xclks port e i/o pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 2.3.9 pe6 / modb / ipipe1 port e i/o pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 2.3.10 pe5 / moda / ipipe0 port e i/o pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 2.3.11 pe4 / eclk port e i/o pin [4] / e-clock output . . . . . . . . . . . . . . . . . . . . . . . . 60 2.3.12 pe3 / lstrb port e i/o pin [3] / low-byte strobe (lstrb). . . . . . . . . . . . . . 60 2.3.13 pe2 / r/w port e i/o pin [2] / read/write. . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 2.3.14 pe1 / irq port e input pin [1] / maskable interrupt pin . . . . . . . . . . . . . . . . . 61 2.3.15 pe0 / xirq port e input pin [0] / non maskable interrupt pin . . . . . . . . . . . . 61 2.3.16 pad[7:0] / an[7:0] port ad i/o pins [7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 2.3.17 pp[7] / kwp[7] port p i/o pin [7]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 2.3.18 pp[6] / kwp[6]/romctl port p i/o pin [6] . . . . . . . . . . . . . . . . . . . . . . . . . . 61 2.3.19 pp[5:0] / kwp[5:0] / pw[5:0] port p i/o pins [5:0] . . . . . . . . . . . . . . . . . . . . . 62 device user guide 9s12c128dgv1/d v01.05 4 2.3.20 pj[7:6] / kwj[7:6] port j i/o pins [7:6] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 2.3.21 pm5 / sck port m i/o pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 2.3.22 pm4 / mosi port m i/o pin 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 2.3.23 pm3 / ss port m i/o pin 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 2.3.24 pm2 / miso port m i/o pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 2.3.25 pm1 / txcan port m i/o pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 2.3.26 pm0 / rxcan port m i/o pin 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 2.3.27 ps[3:2] port s i/o pins [3:2] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 2.3.28 ps1 / txd port s i/o pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 2.3.29 ps0 / rxd port s i/o pin 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 2.3.30 ppt[7:5] / ioc[7:5] port t i/o pins [7:5] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 2.3.31 pt[4:0] / ioc[4:0] / pw[4:0] port t i/o pins [4:0] . . . . . . . . . . . . . . . . . . . . . . . 63 2.4 power supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 2.4.1 vddx,vssx power & ground pins for i/o drivers . . . . . . . . . . . . . . . . . . . . . 63 2.4.2 vddr, vssr power & ground pins for i/o drivers & for internal voltage regulator 63 2.4.3 vdd1, vdd2, vss1, vss2 internal logic power pins . . . . . . . . . . . . . . . . . . 63 2.4.4 vdda, vssa power supply pins for atd and vreg . . . . . . . . . . . . . . . . . . 64 2.4.5 vrh, vrl atd reference voltage input pins . . . . . . . . . . . . . . . . . . . . . . . . 64 2.4.6 vddpll, vsspll power supply pins for pll . . . . . . . . . . . . . . . . . . . . . . . . 64 section 3 system clock description section 4 modes of operation 4.1 overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 5 4.2 chip configuration summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 4.3 security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 4.3.1 securing the microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 4.3.2 operation of the secured microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 4.3.3 unsecuring the microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 4.4 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 4.4.1 stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 4.4.2 pseudo stop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 4.4.3 wait . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 4.4.4 run. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 section 5 resets and interrupts device user guide 9s12c128dgv1/d v01.05 5 5.1 overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 8 5.2 vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 5.2.1 vector table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 5.3 resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 5.3.1 reset summary table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 5.3.2 effects of reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 section 6 hcs12 core block description 6.1 device-specific information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 6.1.1 ppage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 6.1.2 bdm alternate clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 6.1.3 extended address range emulation implications . . . . . . . . . . . . . . . . . . . . . . . . 71 section 7 voltage regulator (vreg) block description 7.1 device-specific information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 7.1.1 vregen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 7.1.2 vdd1, vdd2, vss1, vss2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 section 8 recommended printed circuit board layout section 9 clock reset generator (crg) block description 9.1 device-specific information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 9.1.1 xclks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 section 10 oscillator (osc) block description section 11 timer (tim) block description section 12 analog to digital converter (atd) block description 12.1 device-specific information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 12.1.1 vrl (voltage reference low). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 section 13 serial communications interface (sci) block description section 14 serial peripheral interface (spi) block description section 15 flash block description device user guide 9s12c128dgv1/d v01.05 6 section 16 ram block description section 17 pulse width modulator (pwm) block description section 18 mscan block description section 19 port integration module (pim) block description appendix a electrical characteristics a.1 general. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 a.1.1 parameter classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 a.1.2 power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 a.1.3 pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 a.1.4 current injection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 a.1.5 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 a.1.6 esd protection and latch-up immunity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 a.1.7 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 a.1.8 power dissipation and thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 87 a.1.9 i/o characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 a.1.10 supply currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 appendix b electrical specifications b.1 voltage regulator operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 b.2 chip power-up and lvi/lvr graphical explanation . . . . . . . . . . . . . . . . . . . . . . . . . 96 b.3 output loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 b.3.1 resistive loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 b.3.2 capacitive loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 b.4 atd characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 b.4.1 atd operating characteristics in 5v range . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 b.4.2 atd operating characteristics in 3.3v range . . . . . . . . . . . . . . . . . . . . . . . . . . 99 b.4.3 factors influencing accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 b.4.4 atd accuracy (5v range) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 b.4.5 atd accuracy (3.3v range) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 b.5 nvm, flash and eeprom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 b.5.1 nvm timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 b.5.2 nvm reliability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 device user guide 9s12c128dgv1/d v01.05 7 b.6 reset, oscillator and pll. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 b.6.1 startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 b.6.2 oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 b.6.3 phase locked loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 b.7 mscan. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 b.8 spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 appendix c electrical specifications c.1 master mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 c.2 slave mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 c.3 external bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 c.3.1 general muxed bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 appendix d package information d.1 general. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 7 d.2 80-pin qfp package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 d.3 52-pin lqfp package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 d.4 48-pin lqfp package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 appendix e emulation information e.1 general. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1 e.1.1 pk[2:0] / xaddr[16:14]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 e.2 112-pin lqfp package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 device user guide 9s12c128dgv1/d v01.05 8 device user guide 9s12c128dgv1/d v01.05 9 list of figures figure 0-1 order part number coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 1-1 mc9s12c-family block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 1-2 mc9s12c128 and mc9s12gc128 user configurable memory map . . . . . . 29 figure 1-3 mc9s12c96 user configurable memory map . . . . . . . . . . . . . . . . . . . . . . . 30 figure 1-4 mc9s12c64 and mc9s12gc64 user configurable memory map. . . . . . . . 31 figure 1-5 mc9s12c32 and mc9s12gc32 user configurable memory map. . . . . . . . 32 figure 1-6 mc9s12gc16 user configurable memory map . . . . . . . . . . . . . . . . . . . . . . 33 figure 2-1 pin assignments in 80 qfp for mc9s12c-family . . . . . . . . . . . . . . . . . . . . 52 figure 2-2 pin assignments in 52 lqfp for mc9s12c-family. . . . . . . . . . . . . . . . . . . . 53 figure 2-3 pin assignments in 48 lqfp for mc9s12c-family . . . . . . . . . . . . . . . . . . . 54 figure 2-4 pll loop filter connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 figure 2-5 colpitts oscillator connections (pe7=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 figure 2-6 pierce oscillator connections (pe7=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 figure 2-7 external clock connections (pe7=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 figure 3-1 clock connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 figure 8-1 recommended pcb layout (48 lqfp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 figure 8-2 recommended pcb layout (52 lqfp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 figure 8-3 recommended pcb layout (80 qfp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 figure 8-4 recommended pcb layout for 48 lqfp pierce oscillator . . . . . . . . . . . . . 77 figure 8-5 recommended pcb layout for 52 lqfp pierce oscillator . . . . . . . . . . . . . 78 figure 8-6 recommended pcb layout for 80qfp pierce oscillator . . . . . . . . . . . . . . . 79 figure b-1 voltage regulator - chip power-up and voltage drops (not scaled) . . . . . 96 figure b-2 atd accuracy definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 figure b-3 basic pll functional diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 figure b-4 jitter definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 figure b-5 maximum bus clock jitter approximation . . . . . . . . . . . . . . . . . . . . . . . . . . 114 figure c-1 spi master timing (cpha=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 figure c-2 spi master timing (cpha=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 figure c-3 spi slave timing (cpha=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 figure c-4 spi slave timing (cpha=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 figure c-5 general external bus timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 figure d-1 80-pin qfp mechanical dimensions (case no. 841b) . . . . . . . . . . . . . . . . 128 figure d-2 52-pin lqfp mechanical dimensions (case no. 848d-03) . . . . . . . . . . . . 129 device user guide 9s12c128dgv1/d v01.05 10 figure d-3 48-pin lqfp mechanical dimensions (case no.932-03 issue f) . . . . . . 130 figure 19-1 pin assignments in 112-pin lqfp. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 figure 19-2 112-pin lqfp mechanical dimensions (case no. 987)80-pin qfp mechanical di- mensions (case no. 841b)133 device user guide 9s12c128dgv1/d v01.05 11 list of tables table 0-2 mc9s12c-family package option summary . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 0-1 list of mc9s12c and mc9s12gc family members. . . . . . . . . . . . . . . . . . . . 15 table 0-3 mc9s12c-family part number coding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 0-4 mc9s12gc-family part number coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 0-5 document references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 1-1 device register map overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 $0000 - $000fmebi map 1 of 3 (hcs12 multiplexed external bus interface) 34 $0010 - $0014 mmc map 1 of 4 (hcs12 module mapping control) 34 $0018 - $0018 miscellaneous peripherals (device user guide) 35 $0019 - $0019 vreg3v3 (voltage regulator) 35 $0015 - $0016 int map 1 of 2 (hcs12 interrupt) 35 $0017 - $0017mmc map 2 of 4 (hcs12 module mapping control) 35 $001a - $001b miscellaneous peripherals (device user guide) 35 $001c - $001d mmc map 3 of 4 (hcs12 module mapping control, 36 device user guide) 36 $001e - $001e mebi map 2 of 3 (hcs12 multiplexed external bus interface) 36 $001f - $001f int map 2 of 2 (hcs12 interrupt) 36 $0020 - $002f dbg (including bkp) map 1 of 1 (hcs12 debug) 36 $0030 - $0031 mmc map 4 of 4 (hcs12 module mapping control) 37 $0032 - $0033 mebi map 3 of 3 (hcs12 multiplexed external bus interface) 37 $0034 - $003f crg (clock and reset generator) 37 $0040 - $006f tim (timer 16 bit 8 channels) 38 $0070 - $007f reserved 40 $0080 - $009f atd (analog to digital converter 10 bit 8 channel) 40 $00a0 - $00c7 reserved 41 $00d0 - $00d7 reserved 42 $00c8 - $00cf sci (asynchronous serial interface) 42 $00d8 - $00df spi (serial peripheral interface) 42 $00e0 - $00ff pwm (pulse width modulator) 43 $0100 - $010f flash control register 44 $0110 - $013f reserved 45 $0140 - $017f can (motorola scalable can - mscan) 45 table 1-2 detailed mscan foreground receive and transmit buffer layout. . . . . . . . 46 device user guide 9s12c128dgv1/d v01.05 12 $0180 - $023f reserved 47 $0240 - $027f pim (port interface module) 47 $0280 - $03ff reserved space 50 table 1-3 assigned part id numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 1-4 memory size registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 2-1 signal properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 2-2 mc9s12c-family power and ground connection summary . . . . . . . . . . . . . 64 table 4-1 mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 4-2 clock selection based on pe7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 5-1 interrupt vector locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 5-2 reset summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 6-1 device specific flash page mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 8-1 recommended external component values. . . . . . . . . . . . . . . . . . . . . . . . . . 73 table a-1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 table a-2 esd and latch-up test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 table a-3 esd and latch-up protection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 86 table a-4 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 table a-5 thermal package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 table a-6 5v i/o characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 table a-7 3.3v i/o characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 table a-8 supply current characteristics for mc9s12c32 . . . . . . . . . . . . . . . . . . . . . . . 93 table a-9 supply current characteristics for mc9s12c64,mc9s12c96,mc9s12c128 94 table b-1 voltage regulator electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 table b-2 voltage regulator - capacitive loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 table b-3 atd operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 table b-4 atd operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 table b-5 atd electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 table b-6 atd conversion performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 table b-7 atd conversion performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 table b-8 nvm timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 table b-9 nvm reliability characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 table b-10 startup characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 table b-11 oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 table b-12 pll characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 table b-13 mscan wake-up pulse characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 table c-1 measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 device user guide 9s12c128dgv1/d v01.05 13 table c-2 spi master mode timing characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 table c-3 spi slave mode timing characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 table c-4 expanded bus timing characteristics (5v range). . . . . . . . . . . . . . . . . . . . 124 table c-5 expanded bus timing characteristics (3.3v range) . . . . . . . . . . . . . . . . . . 125 device user guide 9s12c128dgv1/d v01.05 14 device user guide 9s12c128dgv1/d v01.05 15 preface the device user guide provides information about the mc9s12c-family as well the mc9s12gc-family devices made up of standard hcs12 blocks and the hcs12 processor core. this document is part of the customer documentation. a complete set of device manuals also includes the hcs12 core user guide and all the individual block user guides of the implemented modules. in an effort to reduce redundancy all module specific information is located only in the respective block user guide. if applicable, special implementation details of the module are given in the block description sections of this document. the c-family and the gc-family offer an extensive range of package, temperature and speed options. the members of the gc-family do not feature a can module. table 0-1 shows a feature overview of the mc9s12c and mc9s12gc family members. table 0-2 summarizes the package option and size configuration. table 0-3 lists the part number coding based on the package, speed and temperature and preliminary die options for the c-family. table 0-4 lists the part number coding based on the package, speed and temperature and preliminary die options for the gc-family. table 0-2 mc9s12c-family package option summary table 0-1 list of mc9s12c and mc9s12gc family members flash ram device can sci spi a/d pwm timer 128k 4k mc9s12c128 1 1 1 8ch 6ch 8ch mc9s12gc128 1 1 8ch 6ch 8ch 96k 4k mc9s12c96 1 1 1 8ch 6ch 8ch 64k 4k mc9s12c64 1 1 1 8ch 6ch 8ch mc9s12gc64 1 1 8ch 6ch 8ch 32k 2k mc9s12c32 1 1 1 8ch 6ch 8ch mc9s12gc32 1 1 8ch 6ch 8ch 16k 1k mc9s12gc16 1 1 8ch 6ch 8ch package device part number mask 1 set temp. 2 options flash ram i/o 3 , 4 48lqfp mc9s12c128 mc9s12c128 0l09s m, v, c 128k 4k 31 52lqfp mc9s12c128 mc9s12c128 0l09s m, v, c 35 80qfp mc9s12c128 mc9s12c128 0l09s m, v, c 60 48lqfp mc9s12c96 mc9s12c96 tbd m, v, c 96k 4k 31 52lqfp mc9s12c96 mc9s12c96 tbd m, v, c 35 80qfp mc9s12c96 mc9s12c96 tbd m, v, c 60 device user guide 9s12c128dgv1/d v01.05 16 figure 0-1 order part number coding table 0-3 mc9s12c-family part number coding 48lqfp mc9s12c64 mc9s12c64 tbd m, v, c 64k 4k 31 52lqfp mc9s12c64 mc9s12c64 tbd m, v, c 35 80qfp mc9s12c64 mc9s12c64 tbd m, v, c 60 48lqfp mc9s12c32 mc9s12c32 1l45j m, v, c 32k 2k 31 52lqfp mc9s12c32 mc9s12c32 1l45j m, v, c 35 80qfp mc9s12c32 mc9s12c32 1l45j m, v, c 60 48lqfp mc9s12gc128 mc9s12gc128 0l09s m, v, c 128k 4k 31 52lqfp mc9s12gc128 mc9s12gc128 0l09s m, v, c 35 80qfp mc9s12gc128 mc9s12gc128 0l09s m, v, c 60 48lqfp mc9s12gc128 mc9s12gc64 tbd m, v, c 64k 4k 31 52lqfp mc9s12gc128 mc9s12gc64 tbd m, v, c 35 80qfp mc9s12gc128 mc9s12gc64 tbd m, v, c 60 48lqfp mc9s12gc32 mc9s12gc32 1l45j m, v, c 32k 2k 31 52lqfp mc9s12gc32 mc9s12gc32 1l45j m, v, c 35 80qfp mc9s12gc32 mc9s12gc32 1l45j m, v, c 60 48lqfp mc9s12gc16 mc9s12gc16 1l45j m, v, c 16k 2k 31 52lqfp mc9s12gc16 mc9s12gc16 1l45j m, v, c 35 80qfp mc9s12gc16 mc9s12gc16 1l45j m, v, c 60 notes : 1. maskset dependent errata can be accessed at http://e-www.motorola.com/wbapp/sps/site/prod_summary.jsp 2. c: t a = 85?c, f = 25mhz. v: t a =105?c, f = 25mhz. m: t a = 125?c, f = 25mhz 3. all c-family derivatives feature 1 can, 1 sci, 1 spi, an 8-channel a/d, a 6-channel pwm and an 8 channel timer. the gc-family members do not have the can module 4. i/o is the sum of ports capable to act as digital input or output. part number mask set temp. package speed description mc9s12c128cfa16 tbd -40?c, 85?c 48lqfp 16mhz c128 die package device part number mask 1 set temp. 2 options flash ram i/o 3 , 4 mc9s12 c32 ( p) c fu 25 package option temperature option device title controller famil y temperature options c = -40?c to 85?c v = -40?c to 105?c m = -40?c to 125?c package options fu = 80qfp pb = 52lqfp fa = 48lqfp speed option speed options 25 = 25mhz bus 16 = 16mhz bus preliminary option device user guide 9s12c128dgv1/d v01.05 17 mc9s12c128cpb16 tbd -40?c, 85?c 52lqfp 16mhz c128 die mc9s12c128cfu16 tbd -40?c, 85?c 80qfp 16mhz c128 die mc9s12c128vfa16 tbd -40?c,105?c 48lqfp 16mhz c128 die mc9s12c128vpb16 tbd -40?c,105?c 52lqfp 16mhz c128 die mc9s12c128vfu16 tbd -40?c, 105?c 80qfp 16mhz c128 die mc9s12c128mfa16 tbd -40?c,125?c 48lqfp 16mhz c128 die mc9s12c128mpb16 tbd -40?c,125?c 52lqfp 16mhz c128 die mc9s12c128mfu16 tbd -40?c, 125?c 80qfp 16mhz c128 die mc9s12c128cfa25 tbd -40?c, 85?c 48lqfp 25mhz c128 die mc9s12c128cpb25 tbd -40?c, 85?c 52lqfp 25mhz c128 die mc9s12c128cfu25 tbd -40?c, 85?c 80qfp 25mhz c128 die mc9s12c128vfa25 tbd -40?c,105?c 48lqfp 25mhz c128 die mc9s12c128vpb25 tbd -40?c,105?c 52lqfp 25mhz c128 die mc9s12c128vfu25 tbd -40?c, 105?c 80qfp 25mhz c128 die mc9s12c128mfa25 tbd -40?c,125?c 48lqfp 25mhz c128 die mc9s12c128mpb25 tbd -40?c,125?c 52lqfp 25mhz c128 die mc9s12c128mfu25 tbd -40?c, 125?c 80qfp 25mhz c128 die mc9s12c96pcfa16 0l09s -40?c, 85?c 48lqfp 16mhz preliminary c96 using c128 die mc9s12c96pcpb16 0l09s -40?c, 85?c 52lqfp 16mhz preliminary c96 using c128 die mc9s12c96pcfu16 0l09s -40?c, 85?c 80qfp 16mhz preliminary c96 using c128 die mc9s12c96cfa16 tbd -40?c, 85?c 48lqfp 16mhz final c96 using c96 die mc9s12c96cpb16 tbd -40?c, 85?c 52lqfp 16mhz final c96 using c96 die mc9s12c96cfu16 tbd -40?c, 85?c 80qfp 16mhz final c96 using c96 die mc9s12c96pvfa16 0l09s -40?c, 105?c 48lqfp 16mhz preliminary c96 using c128 die mc9s12c96pvpb16 0l09s -40?c, 105?c 52lqfp 16mhz preliminary c96 using c128 die mc9s12c96pvfu16 0l09s -40?c, 105?c 80qfp 16mhz preliminary c96 using c128 die mc9s12c96vfa16 tbd -40?c,105?c 48lqfp 16mhz final c96 using c96 die mc9s12c96vpb16 tbd -40?c,105?c 52lqfp 16mhz final c96 using c96die mc9s12c96vfu16 tbd -40?c, 105?c 80qfp 16mhz final c96 using c96 die mc9s12c96pmfa16 0l09s -40?c, 125?c 48lqfp 16mhz preliminary c96 using c128 die mc9s12c96pmpb16 0l09s -40?c, 125?c 52lqfp 16mhz preliminary c96 using c128 die mc9s12c96pmfu16 0l09s -40?c, 125?c 80qfp 16mhz preliminary c96 using c128 die mc9s12c96mfa16 tbd -40?c,125?c 48lqfp 16mhz final c96 using c96 die mc9s12c96mpb16 tbd -40?c,125?c 52lqfp 16mhz final c96 using c96 die mc9s12c96mfu16 tbd -40?c, 125?c 80qfp 16mhz final c96 using c96 die mc9s12c96pcfa25 0l09s -40?c, 85?c 48lqfp 25mhz preliminary c96 using c128 die mc9s12c96pcpb25 0l09s -40?c, 85?c 52lqfp 25mhz preliminary c96 using c128 die mc9s12c96pcfu25 0l09s -40?c, 85?c 80qfp 25mhz preliminary c96 using c128 die mc9s12c96cfa25 tbd -40?c, 85?c 48lqfp 25mhz final c96 using c96 die mc9s12c96cpb25 tbd -40?c, 85?c 52lqfp 25mhz final c96 using c96 die mc9s12c96cfu25 tbd -40?c, 85?c 80qfp 25mhz final c96 using c96 die mc9s12c96pvfa25 0l09s -40?c, 105?c 48lqfp 25mhz preliminary c96 using c128 die mc9s12c96pvpb25 0l09s -40?c, 105?c 52lqfp 25mhz preliminary c96 using c128 die mc9s12c96pvfu25 0l09s -40?c, 105?c 80qfp 25mhz preliminary c96 using c128 die part number mask set temp. package speed description device user guide 9s12c128dgv1/d v01.05 18 mc9s12c96vfa25 tbd -40?c,105?c 48lqfp 25mhz final c96 using c96 die mc9s12c96vpb25 tbd -40?c,105?c 52lqfp 25mhz final c96 using c96 die mc9s12c96vfu25 tbd -40?c, 105?c 80qfp 25mhz final c96 using c96 die mc9s12c96pmfa25 0l09s -40?c, 125?c 48lqfp 25mhz preliminary c96 using c128 die mc9s12c96pmpb25 0l09s -40?c, 125?c 52lqfp 25mhz preliminary c96 using c128 die mc9s12c96pmfu25 0l09s -40?c, 125?c 80qfp 25mhz preliminary c96 using c128 die mc9s12c96mfa25 tbd -40?c,125?c 48lqfp 25mhz final c96 using c96 die mc9s12c96mpb25 tbd -40?c,125?c 52lqfp 25mhz final c96 using c96 die mc9s12c96mfu25 tbd -40?c, 125?c 80qfp 25mhz final c96 using c96 die mc9s12c64pcfa16 0l09s -40?c, 85?c 48lqfp 16mhz preliminary c64 using c128 die mc9s12c64pcpb16 0l09s -40?c, 85?c 52lqfp 16mhz preliminary c64 using c128 die mc9s12c64pcfu16 0l09s -40?c, 85?c 80qfp 16mhz preliminary c64 using c128 die mc9s12c64cfa16 tbd -40?c, 85?c 48lqfp 16mhz final c64 using c64 die mc9s12c64cpb16 tbd -40?c, 85?c 52lqfp 16mhz final c64 using c64 die mc9s12c64cfu16 tbd -40?c, 85?c 80qfp 16mhz final c64 using c64 die mc9s12c64pvfa16 0l09s -40?c, 105?c 48lqfp 16mhz preliminary c64 using c128 die mc9s12c64pvpb16 0l09s -40?c, 105?c 52lqfp 16mhz preliminary c64 using c128 die mc9s12c64pvfu16 0l09s -40?c, 105?c 80qfp 16mhz preliminary c64 using c128 die mc9s12c64vfa16 tbd -40?c,105?c 48lqfp 16mhz final c64 using c64 die mc9s12c64vpb16 tbd -40?c,105?c 52lqfp 16mhz final c64 using c64 die mc9s12c64vfu16 tbd -40?c, 105?c 80qfp 16mhz final c64 using c64 die mc9s12c64pmfa16 0l09s -40?c, 125?c 48lqfp 16mhz preliminary c64 using c128 die mc9s12c64pmpb16 0l09s -40?c, 125?c 52lqfp 16mhz preliminary c64 using c128 die mc9s12c64pmfu16 0l09s -40?c, 125?c 80qfp 16mhz preliminary c64 using c128 die mc9s12c64mfa16 tbd -40?c,125?c 48lqfp 16mhz final c64 using c64 die mc9s12c64mpb16 tbd -40?c,125?c 52lqfp 16mhz final c64 using c64 die mc9s12c64mfu16 tbd -40?c, 125?c 80qfp 16mhz final c64 using c64 die mc9s12c64pcfa25 0l09s -40?c, 85?c 48lqfp 25mhz preliminary c64 using c128 die mc9s12c64pcpb25 0l09s -40?c, 85?c 52lqfp 25mhz preliminary c64 using c128 die mc9s12c64pcfu25 0l09s -40?c, 85?c 80qfp 25mhz preliminaryc64 using c128 die mc9s12c64cfa25 tbd -40?c, 85?c 48lqfp 25mhz final c64 using c64 die mc9s12c64cpb25 tbd -40?c, 85?c 52lqfp 25mhz final c64 using c64 die mc9s12c64cfu25 tbd -40?c, 85?c 80qfp 25mhz final c64 using c64 die mc9s12c64pvfa25 0l09s -40?c, 105?c 48lqfp 25mhz preliminary c64 using c128 die mc9s12c64pvpb25 0l09s -40?c, 105?c 52lqfp 25mhz preliminary c64 using c128 die mc9s12c64pvfu25 0l09s -40?c, 105?c 80qfp 25mhz preliminary c64 using c128 die mc9s12c64vfa25 tbd -40?c,105?c 48lqfp 25mhz final c64 using c64 die mc9s12c64vpb25 tbd -40?c,105?c 52lqfp 25mhz final c64 using c64 die mc9s12c64vfu25 tbd -40?c, 105?c 80qfp 25mhz final c64 using c64 die mc9s12c64pmfa25 0l09s -40?c, 125?c 48lqfp 25mhz preliminary c64 using c128 die mc9s12c64pmpb25 0l09s -40?c, 125?c 52lqfp 25mhz preliminary c64 using c128 die mc9s12c64pmfu25 0l09s -40?c, 125?c 80qfp 25mhz preliminary c64 using c128 die mc9s12c64mfa25 tbd -40?c,125?c 48lqfp 25mhz final c64 using c64 die mc9s12c64mpb25 tbd -40?c,125?c 52lqfp 25mhz final c64 using c64 die part number mask set temp. package speed description device user guide 9s12c128dgv1/d v01.05 19 table 0-4 mc9s12gc-family part number coding mc9s12c64mfu25 tbd -40?c, 125?c 80qfp 25mhz final c64 using c64 die mc9s12c32cfa16 1l45j -40?c, 85?c 48lqfp 16mhz c32 die mc9s12c32cpb16 1l45j -40?c, 85?c 52lqfp 16mhz c32 die mc9s12c32cfu16 1l45j -40?c, 85?c 80qfp 16mhz c32 die mc9s12c32vfa16 1l45j -40?c,105?c 48lqfp 16mhz c32 die mc9s12c32vpb16 1l45j -40?c,105?c 52lqfp 16mhz c32 die mc9s12c32vfu16 1l45j -40?c, 105?c 80qfp 16mhz c32 die mc9s12c32mfa16 1l45j -40?c,125?c 48lqfp 16mhz c32 die mc9s12c32mpb16 1l45j -40?c,125?c 52lqfp 16mhz c32 die mc9s12c32mfu16 1l45j -40?c, 125?c 80qfp 16mhz c32 die mc9s12c32cfa25 1l45j -40?c, 85?c 48lqfp 25mhz c32 die mc9s12c32cpb25 1l45j -40?c, 85?c 52lqfp 25mhz c32 die mc9s12c32cfu25 1l45j -40?c, 85?c 80qfp 25mhz c32 die mc9s12c32vfa25 1l45j -40?c,105?c 48lqfp 25mhz c32 die mc9s12c32vpb25 1l45j -40?c,105?c 52lqfp 25mhz c32 die mc9s12c32vfu25 1l45j -40?c, 105?c 80qfp 25mhz c32 die mc9s12c32mfa25 1l45j -40?c,125?c 48lqfp 25mhz c32 die mc9s12c32mpb25 1l45j -40?c,125?c 52lqfp 25mhz c32 die mc9s12c32mfu25 1l45j -40?c, 125?c 80qfp 25mhz c32 die part number mask set temp. package speed description MC9S12GC128PCFA25 0l09s -40?c, 85?c 48lqfp 25mhz preliminary gc128 using c128 die mc9s12gc128pcpb25 0l09s -40?c, 85?c 52lqfp 25mhz preliminary gc128 using c128 die mc9s12gc128pcfu25 0l09s -40?c, 85?c 80qfp 25mhz preliminary gc128 using c128 die mc9s12gc128cfa25 tbd -40?c, 85?c 48lqfp 25mhz final gc128 using gc128 die mc9s12gc128cpb25 tbd -40?c, 85?c 52lqfp 25mhz final gc128 using gc128 die mc9s12gc128cfu25 tbd -40?c, 85?c 80qfp 25mhz final gc128 using gc128 die mc9s12gc128pvfa25 0l09s -40?c, 105?c 48lqfp 25mhz preliminary gc128 using c128 die mc9s12gc128pvpb25 0l09s -40?c, 105?c 52lqfp 25mhz preliminary gc128 using c128 die mc9s12gc128pvfu25 0l09s -40?c, 105?c 80qfp 25mhz preliminary gc128 using c128 die mc9s12gc128vfa25 tbd -40?c, 105?c 48lqfp 25mhz final gc128 using gc128 die mc9s12gc128vpb25 tbd -40?c, 105?c 52lqfp 25mhz final gc128 using gc128 die mc9s12gc128vfu25 tbd -40?c, 105?c 80qfp 25mhz final gc128 using gc128 die mc9s12gc128pmfa25 0l09s -40?c, 125?c 48lqfp 25mhz preliminary gc128 using c128 die mc9s12gc128pmpb25 0l09s -40?c, 125?c 52lqfp 25mhz preliminary gc128 using c128 die mc9s12gc128pmfu25 0l09s -40?c, 125?c 80qfp 25mhz preliminary gc128 using c128 die mc9s12gc128mfa25 tbd -40?c, 125?c 48lqfp 25mhz final gc128 using gc128 die mc9s12gc128mpb25 tbd -40?c, 125?c 52lqfp 25mhz final gc128 using gc128 die mc9s12gc128mfu25 tbd -40?c, 125?c 80qfp 25mhz final gc128 using gc128 die mc9s12gc64pcfa25 0l09s -40?c, 85?c 48lqfp 25mhz preliminary gc64 using c128 die mc9s12gc64pcpb25 0l09s -40?c, 85?c 52lqfp 25mhz preliminary gc64 using c128 die mc9s12gc64pcfu25 0l09s -40?c, 85?c 80qfp 25mhz preliminary gc64 using c128 die part number mask set temp. package speed description device user guide 9s12c128dgv1/d v01.05 20 mc9s12gc64cfa25 tbd -40?c, 85?c 48lqfp 25mhz final gc64 using gc64 die mc9s12gc64cpb25 tbd -40?c, 85?c 52lqfp 25mhz final gc64 using gc64 die mc9s12gc64cfu25 tbd -40?c, 85?c 80qfp 25mhz final gc64 using gc64 die mc9s12gc64pvfa25 0l09s -40?c, 105?c 48lqfp 25mhz preliminary gc64 using c128 die mc9s12gc64pvpb25 0l09s -40?c, 105?c 52lqfp 25mhz preliminary gc64 using c128 die mc9s12gc64pvfu25 0l09s -40?c, 105?c 80qfp 25mhz preliminary gc64 using c128 die mc9s12gc64vfa25 tbd -40?c, 105?c 48lqfp 25mhz final gc64 using gc64 die mc9s12gc64vpb25 tbd -40?c, 105?c 52lqfp 25mhz final gc64 using gc64 die mc9s12gc64vfu25 tbd -40?c, 105?c 80qfp 25mhz final gc64 using gc64 die mc9s12gc64pmfa25 0l09s -40?c, 125?c 48lqfp 25mhz preliminary gc64 using c128 die mc9s12gc64pmpb25 0l09s -40?c, 125?c 52lqfp 25mhz preliminary gc64 using c128 die mc9s12gc64pmfu25 0l09s -40?c, 125?c 80qfp 25mhz preliminary gc64 using c128 die mc9s12gc64mfa25 tbd -40?c, 125?c 48lqfp 25mhz final gc64 using gc64 die mc9s12gc64mpb25 tbd -40?c, 125?c 52lqfp 25mhz final gc64 using gc64 die mc9s12gc64mfu25 tbd -40?c, 125?c 80qfp 25mhz final gc64 using gc64 die mc9s12gc32pcfa25 1l45j -40?c, 85?c 48lqfp 25mhz preliminary gc32 using c32 die mc9s12gc32pcpb25 1l45j -40?c, 85?c 52lqfp 25mhz preliminary gc32 using c32 die mc9s12gc32pcfu25 1l45j -40?c, 85?c 80qfp 25mhz preliminary gc32 using c32 die mc9s12gc32cfa25 tbd -40?c, 85?c 48lqfp 25mhz final gc32 using gc32 die mc9s12gc32cpb25 tbd -40?c, 85?c 52lqfp 25mhz final gc32 using gc32 die mc9s12gc32cfu25 tbd -40?c, 85?c 80qfp 25mhz final gc32 using gc32 die mc9s12gc32pvfa25 1l45j -40?c,105?c 48lqfp 25mhz preliminary gc32 using c32 die mc9s12gc32pvpb25 1l45j -40?c,105?c 52lqfp 25mhz preliminary gc32 using c32 die mc9s12gc32pvfu25 1l45j -40?c, 105?c 80qfp 25mhz preliminary gc32 using c32 die mc9s12gc32vfa25 tbd -40?c,105?c 48lqfp 25mhz final gc32 using gc32 die mc9s12gc32vpb25 tbd -40?c,105?c 52lqfp 25mhz final gc32 using gc32 die mc9s12gc32vfu25 tbd -40?c, 105?c 80qfp 25mhz final gc32 using gc32 die mc9s12gc32pmfa25 1l45j -40?c,125?c 48lqfp 25mhz preliminary gc32 using c32 die mc9s12gc32pmpb25 1l45j -40?c,125?c 52lqfp 25mhz preliminary gc32 using c32 die mc9s12gc32pmfu25 1l45j -40?c, 125?c 80qfp 25mhz preliminary gc32 using c32 die mc9s12gc32mfa25 tbd -40?c,125?c 48lqfp 25mhz final gc32 using gc32 die mc9s12gc32mpb25 tbd -40?c,125?c 52lqfp 25mhz final gc32 using gc32 die mc9s12gc32mfu25 tbd -40?c, 125?c 80qfp 25mhz final gc32 using gc32 die mc9s12gc16pcfa25 1l45j -40?c, 85?c 48lqfp 25mhz preliminary gc16 using c32 die mc9s12gc16pcpb25 1l45j -40?c, 85?c 52lqfp 25mhz preliminary gc16 using c32 die mc9s12gc16pcfu25 1l45j -40?c, 85?c 80qfp 25mhz preliminary gc16 using c32 die mc9s12gc16cfa25 tbd -40?c, 85?c 48lqfp 25mhz final gc16 using gc16 die mc9s12gc16cpb25 tbd -40?c, 85?c 52lqfp 25mhz final gc16 using gc16 die mc9s12gc16cfu25 tbd -40?c, 85?c 80qfp 25mhz final gc16 using gc16 die mc9s12gc16pvfa25 1l45j -40?c,105?c 48lqfp 25mhz preliminary gc16 using c32 die mc9s12gc16pvpb25 1l45j -40?c,105?c 52lqfp 25mhz preliminary gc16 using c32 die mc9s12gc16pvfu25 1l45j -40?c, 105?c 80qfp 25mhz preliminary gc16 using c32 die mc9s12gc16vfa25 tbd -40?c,105?c 48lqfp 25mhz final gc16 using gc16 die mc9s12gc16vpb25 tbd -40?c,105?c 52lqfp 25mhz final gc16 using gc16 die part number mask set temp. package speed description device user guide 9s12c128dgv1/d v01.05 21 table 0-5 document references terminology mc9s12gc16vfu25 tbd -40?c, 105?c 80qfp 25mhz final gc16 using gc16 die mc9s12gc16pmfa25 1l45j -40?c,125?c 48lqfp 25mhz preliminary gc16 using c32 die mc9s12gc16pmpb25 1l45j -40?c,125?c 52lqfp 25mhz preliminary gc16 using c32 die mc9s12gc16pmfu25 1l45j -40?c, 125?c 80qfp 25mhz preliminary gc16 using c32 die mc9s12gc16mfa25 tbd -40?c,125?c 48lqfp 25mhz final gc16 using gc16 die mc9s12gc16mpb25 tbd -40?c,125?c 52lqfp 25mhz final gc16 using gc16 die mc9s12gc16mfu25 tbd -40?c, 125?c 80qfp 25mhz final gc16 using gc16 die user guide 1 notes : 1. for the gc16 refer to the 16k flash, for the c32 and gc32 refer to the 32k flash, for the c64 and gc64 the 64k flash, for the c96 the 96k flash and c128 the 128k flash document. version document order number cpu12 reference manual v02 s12cpuv2/d hcs12 debug (dbg) block guide v01 s12dbgv1/d hcs12 background debug (bdm) block guide v04 s12bdmv4/d hcs12 module mapping control (mmc) block guide v04 s12mmcv4/d hcs12 multiplexed external bus interface (mebi) block guide v03 s12mebiv3/d hcs12 interrupt (int) block guide v01 s12intv1/d analog to digital converter: 10 bit 8 channel (atd_10b8c) block guide v02 s12atd10b8cv2/d clock and reset generator (crg) block guide v04 s12crgv4/d serial communications interface (sci) block guide v02 s12sciv2/d serial peripheral interface (spi) block guide v03 s12spiv3/d motorola scalable can (mscan) block guide 2 2. not available on the gc-family members v02 s12mscanv2/d pulse width modulator: 8 bit, 6 channel (pwm_8b6c) block guide v01 s12pwm8b6v1/d timer: 16 bit, 8 channel (tim_16b8c) block guide v01 s12tim16b8cv1/d voltage regulator (vreg) block guide v02 s12vreg3v3v2/d oscillator (osc) block guide v02 s12oscv2/d port integration module (pim_9c32) block guide v01 s12c32pimv1/d 32kbyte flash eeprom (fts32k) block guide v01 s12fts32kv1/d 64kbyte flash eeprom (fts64k) block guide v01 s12fts64kv1/d 128kbyte flash eeprom (fts128k1) block guide v01 s12fts128k1v1/d acronyms and abbreviations new or invented terms, symbols, and notations part number mask set temp. package speed description device user guide 9s12c128dgv1/d v01.05 22 device user guide 9s12c128dgv1/d v01.05 23 section 1 introduction 1.1 overview the mc9s12c-family and the mc9s12gc-family is a 48/52/80 pin flash-based industrial/automotive network control mcu family. members of the mc9s12c-family and the mc9s12gc-family deliver the power and flexibility of our 16 bit core (cpu12) family to a whole new range of cost and space sensitive, general purpose industrial and automotive network applications. all mc9s12c-family and mc9s12gc-family members are comprised of standard on-chip peripherals including a 16-bit central processing unit (cpu12), up to 128k bytes of flash eeprom, up to 4k bytes of ram, an asynchronous serial communications interface (sci), a serial peripheral interface (spi), an 8-channel 16-bit timer module (tim), a 6-channel 8-bit pulse width modulator (pwm), an 8-channel, 10-bit analog-to-digital converter (adc). the mc9s12c-family members also feature a can 2.0 a, b software compatible module (mscan12). the mc9s12c-family as well as the mc9s12gc-family has full 16-bit data paths throughout. the inclusion of a pll circuit allows power consumption and performance to be adjusted to suit operational requirements. in addition to the i/o ports available in each module, up to 10 dedicated i/o port bits are available with wake-up capability from stop or wait mode. the mc9s12c-family and the mc9s12gc-family devices are available in 48, 52 and 80 pin qfp packages, with the 80 pin version pin compatible to the hcs12 a, b and d- family derivatives. 1.2 features ? 16-bit hcs12 core C hcs12 cpu i. upward compatible with m68hc11 instruction set ii. interrupt stacking and programmers model identical to m68hc11 iii. instruction queue iv. enhanced indexed addressing C mmc (memory map and interface) C int (interrupt control) C bdm (background debug mode) C dbg12 (enhanced debug12 module, including breakpoints and change-of-flow trace buffer) C mebi: multiplexed expansion bus interface (available only in 80 pin package version) ? wake-up interrupt inputs C up to 12-port bits available for wake up interrupt function with digital filtering ? memory options C 16k or 32kbyte flash eeprom (erasable in 512-byte sectors) 64k, 96k or 128kbyte flash eeprom (erasable in 1024-byte sectors) device user guide 9s12c128dgv1/d v01.05 24 C 1k, 2k or 4k byte ram ? analog-to-digital converters C one 8-channel module with 10-bit resolution. C external conversion trigger capability ? available on mc9s12c-family: one 1m bit per second, can 2.0 a, b software compatible module C five receive and three transmit buffers C flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit or 8x8bit C four separate interrupt channels for rx, tx, error and wake-up C low-pass filter wake-up function C loop-back for self test operation ? timer module (tim) C 8-channel timer C each channel configurable as either input capture or output compare C simple pwm mode C modulo reset of timer counter C 16-bit pulse accumulator C external event counting C gated time accumulation ? 6 pwm channels C programmable period and duty cycle C 8-bit 6-channel or 16-bit 3-channel C separate control for each pulse width and duty cycle C center-aligned or left-aligned outputs C programmable clock select logic with a wide range of frequencies C fast emergency shutdown input ? serial interfaces C one asynchronous serial communications interface (sci) C one synchronous serial peripheral interface (spi) ? crg (clock reset generator module) C windowed cop watchdog, C real time interrupt, C clock monitor, device user guide 9s12c128dgv1/d v01.05 25 C pierce or low current colpitts oscillator C phase-locked loop clock frequency multiplier C limp home mode in absence of external clock C low power 0.5 to 16 mhz crystal oscillator reference clock ? operating frequency C 32mhz equivalent to 16mhz bus speed for single chip C 32mhz equivalent to 16mhz bus speed in expanded bus modes C option of 9s12c-family: 50mhz equivalent to 25mhz bus speed C all 9s12gc-family members allow a 50mhz operting frequency. ? internal 2.5v regulator C supports an input voltage range from 2.97v to 5.5v C low power mode capability C includes low voltage reset (lvr) circuitry C includes low voltage interrupt (lvi) circuitry ? 48-pin lqfp, 52-pin lqfp or 80-pin qfp package C up to 58 i/o lines with 5v input and drive capability (80 pin package) C up to 2 dedicated 5v input only lines (irq, xirq) C 5v 8 a/d converter inputs and 5v i/o ? development support C single-wire background debug? mode (bdm) C on-chip hardware breakpoints C enhanced dbg12 debug features 1.3 modes of operation user modes (expanded modes are only available in the 80 pin package version). ? normal and emulation operating modes C normal single-chip mode C normal expanded wide mode C normal expanded narrow mode C emulation expanded wide mode C emulation expanded narrow mode ? special operating modes device user guide 9s12c128dgv1/d v01.05 26 C special single-chip mode with active background debug mode C special test mode (motorola use only) C special peripheral mode (motorola use only) ? low power modes C stop mode C pseudo stop mode C wait mode device user guide 9s12c128dgv1/d v01.05 27 1.4 block diagram figure 1-1 mc9s12c-family block diagram mscan txcan rxcan 16k, 32k, 64k, 96k, 128k byte flash 1k, 2k, 4k byte ram sci vddr vdda vssa vrh vrl atd an2 an6 an0 an7 an1 an3 an4 an5 pad3 pad4 pad5 pad6 pad7 pad0 pad1 pad2 ioc2 ioc6 ioc0 ioc7 ioc1 ioc3 ioc4 ioc5 pt3 pt4 pt5 pt6 pt7 pt0 pt1 pt2 rxd txd sck miso ps3 ps0 ps1 ps2 ss spi ptad ptt ddrt pts ddrs voltage regulator vdd1 vss1 pwm signals shown in bold are not available on the 52 or 48 pin package ddrad vdda vssa timer module vddx vssx vrh vrl vssr reset extal xtal bkgd r/ w modb/ipipe1 xirq noacc/ xclks system integration module (sim) hcs12 periodic interrupt cop watchdog clock monitor background pll vsspll xfc vddpll multiplexed address/data bus multiplexed wide bus irq lstrb/ taglo eclk moda/ipipe0 pa 4 pa 3 pa 2 pa 1 pa 0 pa 7 pa 6 pa 5 test/vpp addr12 addr11 addr10 addr9 addr8 addr15 addr14 addr13 data12 data11 data10 data9 data 8 data15 data14 data13 pb4 pb3 pb2 pb1 pb0 pb7 pb6 pb5 addr4 addr3 addr2 addr1 addr0 addr7 addr6 addr5 data 4 data3 data2 data1 data0 data7 data6 data5 pe3 pe4 pe5 pe6 pe7 pe0 pe1 pe2 ddra ddrb pta ptb ddre pte clock and reset generation module debug12 module vdd2 vss2 signals shown in bold italic are available in the 52, but not the 48 pin package cpu pm3 pm4 pm5 pm0 pm1 pm2 ptm ddrm pw2 pw0 pw1 pw3 pw4 pw5 pp3 pp4 pp5 pp6 pp7 pp0 pp1 pp2 ptp ddrp pj6 pj7 ptj ddrj vdd1,2 vss1,2 vddx vssx internal logic 2.5v vddpll vsspll pll 2.5v i/o driver 5v vdda vssa a/d converter 5v vddr vssr voltage regulator 5v & i/o vrl is bonded internally to vssa for 52 and 48 pin packages mosi module mux keypad interrupt key int modc mscan is not available on the 9s12gc family members device user guide 9s12c128dgv1/d v01.05 28 1.5 device memory map table 1-1 shows the device register map of the mc9s12c-family after reset. the following figures ( figure 1-2 , figure 1-2 , figure 1-3 and figure 1-4 ) illustrate the full device memory map with flash and ram. table 1-1 device register map overview address module size $000 - $017 core (ports a, b, e, modes, inits, test) 24 $018 reserved 1 $019 voltage regulator (vreg) 1 $01a - $01b device id register 2 $01c - $01f core (memsiz, irq, hprio) 4 $020 - $02f core (dbg) 16 $030 - $033 core (ppage 1 ) notes : 1. external memory paging is not supported on this device ( 6.1.1 ppage ). 4 $034 - $03f clock and reset generator (crg) 12 $040 - $06f standard timer module16-bit 8-channels (tim) 48 $070 - $07f reserved 16 $080 - $09f analog to digital convert (atd) 32 $0a0 - $0c7 reserved 40 $0c8 - $0cf serial communications interface (sci) 8 $0d0 - $0d7 reserved 8 $0d8 - $0df serial peripheral interface (spi) 8 $0e0 - $0ff pulse width modulator 8-bit 6 channels (pwm) 32 $100 - $10f flash control register 16 $110 - $13f reserved 48 $140 - $17f motorola scalable can (mscan) 2 2. not available on mc9s12gc-family devices 64 $180 - $23f reserved 192 $240 - $27f port integration module (pim) 64 $280 - $3ff reserved 384 device user guide 9s12c128dgv1/d v01.05 29 figure 1-2 mc9s12c128 and mc9s12gc128 user configurable memory map $0000 $ffff $c000 $8000 $4000 $0400 $ff00 ext normal single chip expanded special single chip vectors vectors $ff00 $ffff bdm (if active) $c000 $ffff 16k fixed flash eeprom $8000 $bfff 16k page window 8 * 16k flash eeprom pages $4000 $7fff 16k fixed flash eeprom $3000 $3fff $0000 $03ff 1k register space mappable to any 2k boundary mappable to any 4k boundary 4k bytes ram $3000 the ?gure shows a useful map, which is not the map out of reset. after reset the map is: $0000 - $03ff: register space $0000 - $0fff: 4k ram (only 3k visible $0400 - $0fff) $0000 $3fff 16k fixed flash eeprom vectors flash erase sector size is 1024 bytes page map $3d $3e $3f ppage device user guide 9s12c128dgv1/d v01.05 30 figure 1-3 mc9s12c96 user configurable memory map $0000 $ffff $c000 $8000 $4000 $0400 $ff00 ext normal single chip expanded special single chip vectors vectors $ff00 $ffff bdm (if active) $c000 $ffff 16k fixed flash eeprom $8000 $bfff 16k page window 6 * 16k flash eeprom pages $4000 $7fff 16k fixed flash eeprom $3000 $3fff $0000 $03ff 1k register space mappable to any 2k boundary mappable to any 4k boundary 4k bytes ram $3000 the ?gure shows a useful map, which is not the map out of reset. after reset the map is: $0000 - $03ff: register space $0000 - $0fff: 4k ram (only 3k visible $0400 - $0fff) $0000 $3fff 16k fixed flash eeprom vectors flash erase sector size is 1024 bytes page map $3d $3e $3f ppage device user guide 9s12c128dgv1/d v01.05 31 figure 1-4 mc9s12c64 and mc9s12gc64 user configurable memory map $0000 $ffff $c000 $8000 $4000 $0400 $ff00 ext normal single chip expanded special single chip vectors vectors $ff00 $ffff bdm (if active) $c000 $ffff 16k fixed flash eeprom $8000 $bfff 16k page window 4 * 16k flash eeprom pages $4000 $7fff 16k fixed flash eeprom $3000 $3fff $0000 $03ff 1k register space mappable to any 2k boundary mappable to any 4k boundary 4k bytes ram $3000 the ?gure shows a useful map, which is not the map out of reset. after reset the map is: $0000 - $03ff: register space $0000 - $0fff: 4k ram (only 3k visible $0400 - $0fff) $0000 $3fff 16k fixed flash eeprom vectors flash erase sector size is 1024 bytes page map $3e $3f ppage $3d device user guide 9s12c128dgv1/d v01.05 32 figure 1-5 mc9s12c32 and mc9s12gc32 user configurable memory map $0000 $ffff $c000 $8000 $4000 $0400 $ff00 ext normal single chip expanded special single chip vectors vectors $ff00 $ffff bdm (if active) $c000 $ffff 16k fixed flash eeprom $8000 $bfff 16k page window 2 * 16k flash eeprom pages $3800 $3fff $0000 $03ff 1k register space mappable to any 2k boundary mappable to any 2k boundary 2k bytes ram $3800 the ?gure shows a useful map, which is not the map out of reset. after reset the map is: $0000 - $03ff: register space $0800 - $0fff: 2k ram vectors flash erase sector size is 512 bytes page map $3e $3f ppage device user guide 9s12c128dgv1/d v01.05 33 figure 1-6 mc9s12gc16 user configurable memory map 1.6 detailed register map the detailed register map of the mc9s12c family is listed in address order below. $0000 $ffff $c000 $8000 $4000 $0400 $ff00 ext normal single chip expanded special single chip vectors vectors $ff00 $ffff bdm (if active) $c000 $ffff 16k fixed flash eeprom $3800 $3fff $0000 $03ff 1k register space mappable to any 2k boundary mappable to any 2k boundary 2k bytes ram $3800 the ?gure shows a useful map, which is not the map out of reset. after reset the map is: $0000 - $03ff: register space $0800 - $0fff: 2k ram vectors flash erase sector size is 512 bytes page map $3f ppage device user guide 9s12c128dgv1/d v01.05 34 $0000 - $000f mebi map 1 of 3 (hcs12 multiplexed external bus interface) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0000 porta read: bit 7 654321 bit 0 write: $0001 portb read: bit 7 654321 bit 0 write: $0002 ddra read: bit 7 654321 bit 0 write: $0003 ddrb read: bit 7 654321 bit 0 write: $0004 reserved read: 00000000 write: $0005 reserved read: 00000000 write: $0006 reserved read: 00000000 write: $0007 reserved read: 00000000 write: $0008 porte read: bit 7 65432 bit 1 bit 0 write: $0009 ddre read: bit 7 6543 bit 2 00 write: $000a pear read: noacce 0 pipoe neclk lstre rdwe 00 write: $000b mode read: modc modb moda 0 ivis 0 emk eme write: $000c pucr read: pupke 00 pupee 00 pupbe pupae write: $000d rdriv read: rdpk 00 rdpe 00 rdpb rdpa write: $000e ebictl read: 0000000 estr write: $000f reserved read: 00000000 write: $0010 - $0014 mmc map 1 of 4 (hcs12 module mapping control) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0010 initrm read: ram15 ram14 ram13 ram12 ram11 00 ramhal write: $0011 initrg read: 0 reg14 reg13 reg12 reg11 000 write: address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 device user guide 9s12c128dgv1/d v01.05 35 $0018 - $0018 miscellaneous peripherals (device user guide) $0019 - $0019 vreg3v3 (voltage regulator) $0012 initee read: ee15 ee14 ee13 ee12 ee11 00 eeon write: $0013 misc read: 0000 exstr1 exstr0 romhm romon write: $0014 reserved read: 00000000 write: $0015 - $0016 int map 1 of 2 (hcs12 interrupt) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0015 itcr read: 0 0 0 wrint adr3 adr2 adr1 adr0 write: $0016 itest read: inte intc inta int8 int6 int4 int2 int0 write: $0017 - $0017 mmc map 2 of 4 (hcs12 module mapping control) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0017 reserved read: 00000000 write: address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0018 reserved read: 00000000 write: address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0019 vregctrl read: 00000lvds lvie lvif write: $001a - $001b miscellaneous peripherals (device user guide) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $001a partidh read: id15 id14 id13 id12 id11 id10 id9 id8 write: $001b partidl read: id7 id6 id5 id4 id3 id2 id1 id0 write: $0010 - $0014 mmc map 1 of 4 (hcs12 module mapping control) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 device user guide 9s12c128dgv1/d v01.05 36 $001c - $001d mmc map 3 of 4 (hcs12 module mapping control, device user guide) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $001c memsiz0 read: reg_sw0 0 eep_sw1 eep_sw0 0 ram_sw2 ram_sw1 ram_sw0 write: $001d memsiz1 read: rom_sw1 rom_sw0 0000 pag_sw1 pag_sw0 write: $001e - $001e mebi map 2 of 3 (hcs12 multiplexed external bus interface) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $001e intcr read: irqe irqen 000000 write: $001f - $001f int map 2 of 2 (hcs12 interrupt) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $001f hprio read: psel7 psel6 psel5 psel4 psel3 psel2 psel1 0 write: $0020 - $002f dbg (including bkp) map 1 of 1 (hcs12 debug) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0020 dbgc1 read dbgen arm trgsel begin dbgbrk 0 capmod - write $0021 dbgsc read af bf cf 0 trg - write $0022 dbgtbh read bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 - write $0023 dbgtbl read bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 - write $0024 dbgcnt read tbf 0 cnt - write $0025 dbgccx read pagsel extcmp - write $0026 dbgcch read bit 15 14 13 12 11 10 9 bit 8 write $0027 dbgccl read bit 7 654321 bit 0 - write $0028 dbgc2 read bkaben full bdm tagab bkcen tagc rwcen rwc bkpct0 write $0029 dbgc3 read bkambh bkambl bkbmbh bkbmbl rwaen rwa rwben rwb bkpct1 write $002a dbgcax read pagsel extcmp bkp0x write $002b dbgcah read bit 15 14 13 12 11 10 9 bit 8 bkp0h write device user guide 9s12c128dgv1/d v01.05 37 $002c dbgcal read bit 7 654321 bit 0 bkp0l write $002d dbgcbx read pagsel extcmp bkp1x write $002e dbgcbh read bit 15 14 13 12 11 10 9 bit 8 bkp1h write $002f dbgcbl read bit 7 654321 bit 0 bkp1l write $0030 - $0031 mmc map 4 of 4 (hcs12 module mapping control) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0030 ppage read: 0 0 pix5 pix4 pix3 pix2 pix1 pix0 write: $0031 reserved read: 00000000 write: $0032 - $0033 mebi map 3 of 3 (hcs12 multiplexed external bus interface) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0032 portk 1 notes : 1. only applicable in special emulation-only bond outs, for emulation of extended memory map. read: bit 7 654321 bit 0 write: $0033 ddrk (1) read: bit 7 654321 bit 0 write: $0034 - $003f crg (clock and reset generator) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0034 synr read: 0 0 syn5 syn4 syn3 syn2 syn1 syn0 write: $0035 refdv read: 0000 refdv3 refdv2 refdv1 refdv0 write: $0036 ctflg test only read: tout7 tout6 tout5 tout4 tout3 tout2 tout1 tout0 write: $0037 crgflg read: rtif prof 0 lockif lock track scmif scm write: $0038 crgint read: rtie 00 lockie 00 scmie 0 write: $0039 clksel read: pllsel pstp syswai roawai pllwai cwai rtiwai copwai write: $003a pllctl read: cme pllon auto acq 0 pre pce scme write: $0020 - $002f dbg (including bkp) map 1 of 1 (hcs12 debug) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 device user guide 9s12c128dgv1/d v01.05 38 $0040 - $006f tim (timer 16 bit 8 channels) $003b rtictl read: 0 rtr6 rtr5 rtr4 rtr3 rtr2 rtr1 rtr0 write: $003c copctl read: wcop rsbck 000 cr2 cr1 cr0 write: $003d forbyp test only read: rtibyp copbyp 0 pllbyp 00 fcm 0 write: $003e ctctl test only read: tctl7 tctl6 tctl5 tctl4 tclt3 tctl2 tctl1 tctl0 write: $003f armcop read: 00000000 write: bit 7 654321 bit 0 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0040 tios read: ios7 ios6 ios5 ios4 ios3 ios2 ios1 ios0 write: $0041 cforc read: 00000000 write: foc7 foc6 foc5 foc4 foc3 foc2 foc1 foc0 $0042 oc7m read: oc7m7 oc7m6 oc7m5 oc7m4 oc7m3 oc7m2 oc7m1 oc7m0 write: $0043 oc7d read: oc7d7 oc7d6 oc7d5 oc7d4 oc7d3 oc7d2 oc7d1 oc7d0 write: $0044 tcnt (hi) read: bit 15 14 13 12 11 10 9 bit 8 write: $0045 tcnt (lo) read: bit 7 654321 bit 0 write: $0046 tscr1 read: ten tswai tsfrz tffca 0000 write: $0047 ttov read: tov7 tov6 tov5 tov4 tov3 tov2 tov1 tov0 write: $0048 tctl1 read: om7 ol7 om6 ol6 om5 ol5 om4 ol4 write: $0049 tctl2 read: om3 ol3 om2 ol2 om1 ol1 om0 ol0 write: $004a tctl3 read: edg7b edg7a edg6b edg6a edg5b edg5a edg4b edg4a write: $004b tctl4 read: edg3b edg3a edg2b edg2a edg1b edg1a edg0b edg0a write: $004c tie read: c7i c6i c5i c4i c3i c2i c1i c0i write: $004d tscr2 read: toi 000 tcre pr2 pr1 pr0 write: $004e tflg1 read: c7f c6f c5f c4f c3f c2f c1f c0f write: $004f tflg2 read: tof 0000000 write: $0034 - $003f crg (clock and reset generator) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 device user guide 9s12c128dgv1/d v01.05 39 $0050 tc0 (hi) read: bit 15 14 13 12 11 10 9 bit 8 write: $0051 tc0 (lo) read: bit 7 654321 bit 0 write: $0052 tc1 (hi) read: bit 15 14 13 12 11 10 9 bit 8 write: $0053 tc1 (lo) read: bit 7 654321 bit 0 write: $0054 tc2 (hi) read: bit 15 14 13 12 11 10 9 bit 8 write: $0055 tc2 (lo) read: bit 7 654321 bit 0 write: $0056 tc3 (hi) read: bit 15 14 13 12 11 10 9 bit 8 write: $0057 tc3 (lo) read: bit 7 654321 bit 0 write: $0058 tc4 (hi) read: bit 15 14 13 12 11 10 9 bit 8 write: $0059 tc4 (lo) read: bit 7 654321 bit 0 write: $005a tc5 (hi) read: bit 15 14 13 12 11 10 9 bit 8 write: $005b tc5 (lo) read: bit 7 654321 bit 0 write: $005c tc6 (hi) read: bit 15 14 13 12 11 10 9 bit 8 write: $005d tc6 (lo) read: bit 7 654321 bit 0 write: $005e tc7 (hi) read: bit 15 14 13 12 11 10 9 bit 8 write: $005f tc7 (lo) read: bit 7 654321 bit 0 write: $0060 pactl read: 0 paen pamod pedge clk1 clk0 paovi pai write: $0061 paflg read: 000000 paovf paif write: $0062 pacnt (hi) read: bit 15 14 13 12 11 10 9 bit 8 write: $0063 pacnt (lo) read: bit 7 654321 bit 0 write: $0064 reserved read: 00000000 write: $0065 reserved read: 00000000 write: $0066 reserved read: 00000000 write: $0067 reserved read: 00000000 write: address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 device user guide 9s12c128dgv1/d v01.05 40 $0070 - $007f reserved $0068 reserved read: 00000000 write: $0069 reserved read: 00000000 write: $006a reserved read: 00000000 write: $006b reserved read: 00000000 write: $006c reserved read: 00000000 write: $006d reserved read: 00000000 write: $006e reserved read: 00000000 write: $006f reserved read: 00000000 write: $0070 - $007f reserved read: 00000000 write: $0080 - $009f atd (analog to digital converter 10 bit 8 channel) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0080 atdctl0 read: 00000000 write: $0081 atdctl1 read: 00000000 write: $0082 atdctl2 read: adpu affc awai etrigle etrigp etrig ascie ascif write: $0083 atdctl3 read: 0 s8c s4c s2c s1c fifo frz1 frz0 write: $0084 atdctl4 read: sres8 smp1 smp0 prs4 prs3 prs2 prs1 prs0 write: $0085 atdctl5 read: djm dsgn scan mult 0 cc cb ca write: $0086 atdstat0 read: scf 0 etorf fifor 0 cc2 cc1 cc0 write: $0087 reserved read: 00000000 write: $0088 atdtest0 read: 00000000 write: $0089 atdtest1 read: 0000000 sc write: $008a reserved read: 00000000 write: address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 device user guide 9s12c128dgv1/d v01.05 41 $00a0 - $00c7 reserved $008b atdstat1 read: ccf7 ccf6 ccf5 ccf4 ccf3 ccf2 ccf1 ccf0 write: $008c reserved read: 00000000 write: $008d atddien read: bit 7 654321 bit 0 write: $008e reserved read: 00000000 write: $008f portad0 read: bit7 654321 bit 0 write: $0090 atddr0h read: bit15 14 13 12 11 10 9 bit8 write: $0091 atddr0l read: bit7 bit6 000000 write: $0092 atddr1h read: bit15 14 13 12 11 10 9 bit8 write: $0093 atddr1l read: bit7 bit6 000000 write: $0094 atddr2h read: bit15 14 13 12 11 10 9 bit8 write: $0095 atddr2l read: bit7 bit6 000000 write: $0096 atddr3h read: bit15 14 13 12 11 10 9 bit8 write: $0097 atddr3l read: bit7 bit6 000000 write: $0098 atddr4h read: bit15 14 13 12 11 10 9 bit8 write: $0099 atddr4l read: bit7 bit6 000000 write: $009a atddr5h read: bit15 14 13 12 11 10 9 bit8 write: $009b atddr5l read: bit7 bit6 000000 write: $009c atddr6h read: bit15 14 13 12 11 10 9 bit8 write: $009d atddr6l read: bit7 bit6 000000 write: $009e atddr7h read: bit15 14 13 12 11 10 9 bit8 write: $009f atddr7l read: bit7 bit6 000000 write: $00a0 - $00c7 reserved read: 00000000 write: $0080 - $009f atd (analog to digital converter 10 bit 8 channel) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 device user guide 9s12c128dgv1/d v01.05 42 $00d0 - $00d7 reserved $00c8 - $00cf sci (asynchronous serial interface) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $00c8 scibdh read: 000 sbr12 sbr11 sbr10 sbr9 sbr8 write: $00c9 scibdl read: sbr7 sbr6 sbr5 sbr4 sbr3 sbr2 sbr1 sbr0 write: $00ca scicr1 read: loops sciswai rsrc m wake ilt pe pt write: $00cb scicr2 read: tie tcie rie ilie te re rwu sbk write: $00cc scisr1 read: tdre tc rdrf idle or nf fe pf write: $00cd scisr2 read: 00000 brk13 txdir raf write: $00ce scidrh read: r8 t8 000000 write: $00cf scidrl read: r7 r6 r5 r4 r3 r2 r1 r0 write: t7 t6 t5 t4 t3 t2 t1 t0 $00d0 - $00d7 reserved read: 00000000 write: $00d8 - $00df spi (serial peripheral interface) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $00d8 spicr1 read: spie spe sptie mstr cpol cpha ssoe lsbfe write: $00d9 spicr2 read: 0 0 0 modfen bidiroe 0 spiswai spc0 write: $00da spibr read: 0 sppr2 sppr1 sppr0 0 spr2 spr1 spr0 write: $00db spisr read: spif 0 sptef modf 0000 write: $00dc reserved read: 00000000 write: $00dd spidr read: bit7 654321 bit0 write: $00de reserved read: 0 0 0 0 0 0 0 0 write: $00df reserved read: 00000000 write: device user guide 9s12c128dgv1/d v01.05 43 $00e0 - $00ff pwm (pulse width modulator) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $00e0 pwme read: 0 0 pwme5 pwme4 pwme3 pwme2 pwme1 pwme0 write: $00e1 pwmpol read: 0 0 ppol5 ppol4 ppol3 ppol2 ppol1 ppol0 write: $00e2 pwmclk read: 0 0 pclk5 pclk4 pclk3 pclk2 pclk1 pclk0 write: $00e3 pwmprclk read: 0 pckb2 pckb1 pckb0 0 pcka2 pcka1 pcka0 write: $00e4 pwmcae read: 0 0 cae5 cae4 cae3 cae2 cae1 cae0 write: $00e5 pwmctl read: 0 con45 con23 con01 pswai pfrz 0 0 write: $00e6 pwmtst test only read: 00000000 write: $00e7 pwmprsc read: 00000000 write: $00e8 pwmscla read: bit 7 6 5 4 3 2 1 bit 0 write: $00e9 pwmsclb read: bit 7 6 5 4 3 2 1 bit 0 write: $00ea pwmscnta read: 00000000 write: $00eb pwmscntb read: 00000000 write: $00ec pwmcnt0 read: bit 7 6 5 4 3 2 1 bit 0 write: 00000000 $00ed pwmcnt1 read: bit 7 6 5 4 3 2 1 bit 0 write: 00000000 $00ee pwmcnt2 read: bit 7 6 5 4 3 2 1 bit 0 write: 00000000 $00ef pwmcnt3 read: bit 7 6 5 4 3 2 1 bit 0 write: 00000000 $00f0 pwmcnt4 read: bit 7 6 5 4 3 2 1 bit 0 write: 00000000 $00f1 pwmcnt5 read: bit 7 6 5 4 3 2 1 bit 0 write: 00000000 $00f2 pwmper0 read: bit 7 6 5 4 3 2 1 bit 0 write: $00f3 pwmper1 read: bit 7 6 5 4 3 2 1 bit 0 write: $00f4 pwmper2 read: bit 7 6 5 4 3 2 1 bit 0 write: $00f5 pwmper3 read: bit 7 6 5 4 3 2 1 bit 0 write: $00f6 pwmper4 read: bit 7 6 5 4 3 2 1 bit 0 write: device user guide 9s12c128dgv1/d v01.05 44 $00f7 pwmper5 read: bit 7 6 5 4 3 2 1 bit 0 write: $00f8 pwmdty0 read: bit 7 6 5 4 3 2 1 bit 0 write: $00f9 pwmdty1 read: bit 7 6 5 4 3 2 1 bit 0 write: $00fa pwmdty2 read: bit 7 6 5 4 3 2 1 bit 0 write: $00fb pwmdty3 read: bit 7 6 5 4 3 2 1 bit 0 write: $00fc pwmdty4 read: bit 7 6 5 4 3 2 1 bit 0 write: $00fd pwmdty5 read: bit 7 6 5 4 3 2 1 bit 0 write: $00fe reserved read: 00000000 write: $00ff reserved read: 00000000 write: $0100 - $010f flash control register address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0100 fclkdiv read: fdivld prdiv8 fdiv5 fdiv4 fdiv3 fdiv2 fdiv1 fdiv0 write: $0101 fsec read: keyen1 keyen0 nv5 nv4 nv3 nv2 sec1 sec0 write: $0102 ftstmod read: 0 0 0 wrall 000 0 write: $0103 fcnfg read: cbeie ccie keyacc 000 bksel1 bksel0 write: $0104 fprot read: fpopen nv6 fphdis fphs1 fphs0 fpldis fpls1 fpls0 write: $0105 fstat read: cbeif ccif pviol accerr 0 blank 00 write: $0106 fcmd read: 0 cmdb6 cmdb5 00 cmdb2 0 cmdb0 write: $0107 reserved for factory test read: 00000000 write: $0108 reserved for factory test read: 00000000 write: $0109 reserved for factory test read: 00000000 write: $010a reserved for factory test read: 00000000 write: $010b reserved for factory test read: 00000000 write: address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 device user guide 9s12c128dgv1/d v01.05 45 $0110 - $013f reserved $010c reserved read: 00000000 write: $010d reserved read: 00000000 write: $010e reserved read: 00000000 write: $010f reserved read: 00000000 write: $0110 - $003f reserved read: 00000000 write: $0140 - $017f can (motorola scalable can - mscan) 1 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0140 canctl0 read: rxfrm rxact cswai synch time wupe slprq initrq write: $0141 canctl1 read: cane clksrc loopb listen 0 wupm slpak initak write: $0142 canbtr0 read: sjw1 sjw0 brp5 brp4 brp3 brp2 brp1 brp0 write: $0143 canbtr1 read: samp tseg22 tseg21 tseg20 tseg13 tseg12 tseg11 tseg10 write: $0144 canrflg read: wupif cscif rstat1 rstat0 tstat1 tstat0 ovrif rxf write: $0145 canrier read: wupie cscie rstate1 rstate0 tstate1 tstate0 ovrie rxfie write: $0146 cantflg read: 00000 txe2 txe1 txe0 write: $0147 cantier read: 00000 txeie2 txeie1 txeie0 write: $0148 cantarq read: 00000 abtrq2 abtrq1 abtrq0 write: $0149 cantaak read: 00000abtak2abtak1abtak0 write: $014a cantbsel read: 00000 tx2 tx1 tx0 write: $014b canidac read: 0 0 idam1 idam0 0 idhit2 idhit1 idhit0 write: $014c reserved read: 00000000 write: $014d reserved read: 00000000 write: $0100 - $010f flash control register address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 device user guide 9s12c128dgv1/d v01.05 46 table 1-2 detailed mscan foreground receive and transmit buffer layout $014e canrxerr read: rxerr7 rxerr6 rxerr5 rxerr4 rxerr3 rxerr2 rxerr1 rxerr0 write: $014f cantxerr read: txerr7 txerr6 txerr5 txerr4 txerr3 txerr2 txerr1 txerr0 write: $0150 - $0153 canidar0 - canidar3 read: ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 write: $0154 - $0157 canidmr0 - canidmr3 read: am7 am6 am5 am4 am3 am2 am1 am0 write: $0158 - $015b canidar4 - canidar7 read: ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 write: $015c - $015f canidmr4 - canidmr7 read: am7 am6 am5 am4 am3 am2 am1 am0 write: $0160 - $016f canrxfg read: foreground receive buffer see table 1-2 write: $0170 - $017f cantxfg read: foreground transmit buffer see table 1-2 write: notes : 1. not available on the mc9s12gc-family members. those memory locations should not be accessed. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $xxx0 extended id read: id28 id27 id26 id25 id24 id23 id22 id21 standard id read: id10 id9 id8 id7 id6 id5 id4 id3 canxridr0 write: $xxx1 extended id read: id20 id19 id18 srr=1 ide=1 id17 id16 id15 standard id read: id2 id1 id0 rtr ide=0 canxridr1 write: $xxx2 extended id read: id14 id13 id12 id11 id10 id9 id8 id7 standard id read: canxridr2 write: $xxx3 extended id read: id6 id5 id4 id3 id2 id1 id0 rtr standard id read: canxridr3 write: $xxx4- $xxxb canxrdsr0 - canxrdsr7 read: db7 db6 db5 db4 db3 db2 db1 db0 write: $xxxc canrxdlr read: dlc3 dlc2 dlc1 dlc0 write: $xxxd reserved read: write: $xxxe canxrtsrh read: tsr15 tsr14 tsr13 tsr12 tsr11 tsr10 tsr9 tsr8 write: $xxxf canxrtsrl read: tsr7 tsr6 tsr5 tsr4 tsr3 tsr2 tsr1 tsr0 write: $xx10 extended id read: id28 id27 id26 id25 id24 id23 id22 id21 canxtidr0 write: standard id read: id10 id9 id8 id7 id6 id5 id4 id3 write: $0140 - $017f can (motorola scalable can - mscan) 1 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 device user guide 9s12c128dgv1/d v01.05 47 $0180 - $023f reserved $0240 - $027f pim (port interface module) $xx11 extended id read: id20 id19 id18 srr=1 ide=1 id17 id16 id15 canxtidr1 write: standard id read: id2 id1 id0 rtr ide=0 write: $xx12 extended id read: id14 id13 id12 id11 id10 id9 id8 id7 canxtidr2 write: standard id read: write: $xx13 extended id read: id6 id5 id4 id3 id2 id1 id0 rtr canxtidr3 write: standard id read: write: $xx14- $xx1b canxtdsr0 - canxtdsr7 read: db7 db6 db5 db4 db3 db2 db1 db0 write: $xx1c canxtdlr read: dlc3 dlc2 dlc1 dlc0 write: $xx1d conxttbpr read: prio7 prio6 prio5 prio4 prio3 prio2 prio1 prio0 write: $xx1e canxttsrh read: tsr15 tsr14 tsr13 tsr12 tsr11 tsr10 tsr9 tsr8 write: $xx1f canxttsrl read: tsr7 tsr6 tsr5 tsr4 tsr3 tsr2 tsr1 tsr0 write: $0180 - $023f reserved read: 00000000 write: $0240 ptt read: ptt7 ptt6 ptt5 ptt4 ptt3 ptt2 ptt1 ptt0 write: $0241 ptit read: ptit7 ptit6 ptit5 ptit4 ptit3 ptit2 ptit1 ptit0 write: $0242 ddrt read: ddrt7 ddrt7 ddrt5 ddrt4 ddrt3 ddrt2 ddrt1 ddrt0 write: $0243 rdrt read: rdrt7 rdrt6 rdrt5 rdrt4 rdrt3 rdrt2 rdrt1 rdrt0 write: $0244 pert read: pert7 pert6 pert5 pert4 pert3 pert2 pert1 pert0 write: $0245 ppst read: ppst7 ppst6 ppst5 ppst4 ppst3 ppst2 ppst1 ppst0 write: $0246 reserved read: 00000000 write: $0247 modrr read: 0 0 0 modrr4 modrr3 modrr2 modrr1 modrr0 write: $0248 pts read: 0000 pts3 pts2 pts1 pts0 write: address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 device user guide 9s12c128dgv1/d v01.05 48 $0249 ptis read: 0000 ptis3 ptis2 ptis1 ptis0 write: $024a ddrs read: 0000 ddrs3 ddrs2 ddrs1 ddrs0 write: $024b rdrs read: 0000 rdrs3 rdrs2 rdrs1 rdrs0 write: $024c pers read: 0000 pers3 pers2 pers1 pers0 write: $024d ppss read: 0000 ppss3 ppss2 ppss1 ppss0 write: $024e woms read: 0000 woms3 woms2 woms1 woms0 write: $024f reserved read: 00000000 write: $0250 ptm read: 0 0 ptm5 ptm4 ptm3 ptm2 ptm1 ptm0 write: $0251 ptim read: 0 0 ptim5 ptim4 ptim3 ptim2 ptim1 ptim0 write: $0252 ddrm read: 0 0 ddrm5 ddrm4 ddrm3 ddrm2 ddrm1 ddrm0 write: $0253 rdrm read: 0 0 rdrm5 rdrm4 rdrm3 rdrm2 rdrm1 rdrm0 write: $0254 perm read: 0 0 perm5 perm4 perm3 perm2 perm1 perm0 write: $0255 ppsm read: 0 0 ppsm5 ppsm4 ppsm3 ppsm2 ppsm1 ppsm0 write: $0256 womm read: 0 0 womm5 womm4 womm3 womm2 womm1 womm0 write: $0257 reserved read: 00000000 write: $0258 ptp read: ptp7 ptp6 ptp5 ptp4 ptp3 ptp2 ptp1 ptp0 write: $0259 ptip read: ptip7 ptip6 ptip5 ptip4 ptip3 ptip2 ptip1 ptip0 write: $025a ddrp read: ddrp7 ddrp7 ddrp5 ddrp4 ddrp3 ddrp2 ddrp1 ddrp0 write: $025b rdrp read: rdrp7 rdrp6 rdrp5 rdrp4 rdrp3 rdrp2 rdrp1 rdrp0 write: $025c perp read: perp7 perp6 perp5 perp4 perp3 perp2 perp1 perp0 write: $025d ppsp read: ppsp7 ppsp6 ppsp5 ppsp4 ppsp3 ppsp2 ppsp1 ppss0 write: $025e piep read: piep7 piep6 piep5 piep4 piep3 piep2 piep1 piep0 write: $025f pifp read: pifp7 pifp6 pifp5 pifp4 pifp3 pifp2 pifp1 pifp0 write: $0260 reserved read: 00000000 write: device user guide 9s12c128dgv1/d v01.05 49 $0261 reserved read: 00000000 write: $0262 reserved read: 00000000 write: $0263 reserved read: 00000000 write: $0264 reserved read: 00000000 write: $0265 reserved read: 00000000 write: $0266 reserved read: 00000000 write: $0267 reserved read: 00000000 write: $0268 ptj read: ptj7 ptj6 000000 write: $0269 ptij read: ptij7 ptij6 000000 write: $026a ddrj read: ddrj7 ddrj7 000000 write: $026b rdrj read: rdrj7 rdrj6 000000 write: $026c perj read: perj7 perj6 000000 write: $026d ppsj read: ppsj7 ppsj6 000000 write: $026e piej read: piej7 piej6 000000 write: $026f pifj read: pifj7 pifj6 000000 write: $0270 ptad read: ptad7 ptad6 ptad5 ptad4 ptad3 ptad2 ptad1 ptad0 write: $0271 ptiad read: ptiad7 ptiad6 ptiad5 ptiad4 ptiad3 ptiad2 ptiad1 ptij7 write: $0272 ddrad read: ddrad7 ddrad6 ddrad5 ddrad4 ddrad3 ddrad2 ddrad1 ddrad0 write: $0273 rdrad read: rdrad7 rdrad6 rdrad5 rdrad4 rdrad3 rdrad2 rdrad1 rdrad0 write: $0274 perad read: perad7 perad6 perad5 perad4 perad3 perad2 perad1 perad0 write: $0275 ppsad read: ppsad7 ppsad6 ppsad5 ppsad4 ppsad3 ppsad2 ppsad1 ppsad0 write: $0276- $027f reserved read: 00000000 write: device user guide 9s12c128dgv1/d v01.05 50 1.7 part id assignments the part id is located in two 8-bit registers partidh and partidl (addresses $001a and $001b after reset). the read-only value is a unique part id for each revision of the chip. table 1-3 shows the assigned part id numbers. the device memory sizes are located in two 8-bit registers memsiz0 and memsiz1 (addresses $001c and $001d after reset). table 1-4 shows the read-only values of these registers. refer to module mapping and control (mmc) block guide for further details. $0280 - $03ff reserved space address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0280 - $2ff reserved read: 00000000 write: $0300 - $03ff unimplemented read: 00000000 write: table 1-3 assigned part id numbers device mask set number part id 1 notes : 1. the coding is as follows: bit 15-12: major family identifier bit 11-8: minor family identifier bit 7-4: major mask set revision number including fab transfers bit 3-0: minor - non full - mask set revision mc9s12c32 0l45j $3300 mc9s12c32 1l45j $3300 mc9s12c32 2l45j $3302 mc9s12c64 tbd tbd mc9s12c96 tbd tbd mc9s12c128 0l09s $3100 mc9s12c128 1l09s $3101 mc9s12gc16 tbd tbd mc9s12gc32 tbd tbd mc9s12gc64 tbd tbd mc9s12gc128 tbd tbd table 1-4 memory size registers device register name value mc9s12gc16 memsiz0 $00 memsiz1 $80 device user guide 9s12c128dgv1/d v01.05 51 mc9s12c32, mc9s12gc32 memsiz0 $00 memsiz1 $80 mc9s12c64, mc9s12gc64 memsiz0 $01 memsiz1 $c0 mc9s12c96 memsiz0 $01 memsiz1 $c0 mc9s12c128, mc9s12gc128 memsiz0 $01 memsiz1 $c0 table 1-4 memory size registers device register name value device user guide 9s12c128dgv1/d v01.05 52 section 2 signal description 2.1 device pinout figure 2-1 pin assignments in 80 qfp for mc9s12c-family 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 mc9s12c-family mc9s12gc-family vrh vdda pad07/an07 pad06/an06 pad05/an05 pad04/an04 pad03/an03 pad02/an02 pad01/an01 pad00/an00 vss2 vdd2 pa7/addr15/data15 pa6/addr14/data14 pa5/addr13/data13 pa4/addr12/data12 pa3/addr11/data11 pa2/addr10/data10 pa1/addr9/data9 pa0/addr8/data8 pp4/kwp4/pw4 pp5/kwp5/pw5 pp7/kwp7 vddx vssx pm0/rxcan pm1/txcan pm2/miso pm3/ ss pm4/mosi pm5/sck pj6/kwj6 pj7/kwj7 pp6/kwp6/romctl ps3 ps2 ps1/txd ps0/rxd vssa vrl pw3/kwp3/pp3 pw2/kwp2/pp2 pw1/kwp1/pp1 pw0/kwp0/pp0 pw0/ioc0/pt0 pw1/ioc1/pt1 pw2/ioc2/pt2 pw3/ioc3/pt3 vdd1 vss1 pw4/ioc4/pt4 ioc5/pt5 ioc6/pt6 ioc7/pt7 modc/ t a ghi/bkgd addr0/data0/pb0 addr1/data1/pb1 addr2/data2/pb2 addr3/data3/pb3 addr4/data4/pb4 addr5/data5/pb5 addr6/data6/pb6 addr7/data7/pb7 xclks/noacc/pe7 modb/ipipe1/pe6 moda/ipipe0/pe5 eclk/pe4 vssr vddr reset vddpll xfc vsspll extal xtal test/vpp lstrb/ t a glo/pe3 r/ w/pe2 irq/pe1 xirq/pe0 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 signals shown in bold are not available on the 52 or 48 pin package signals shown in bold italic are available in the 52, but not the 48 pin package device user guide 9s12c128dgv1/d v01.05 53 figure 2-2 pin assignments in 52 lqfp for mc9s12c-family mc9s12c-family mc9s12gc-family 1 2 3 4 5 6 7 8 9 10 11 12 13 39 38 37 36 35 34 33 32 31 30 29 28 27 14 15 16 17 18 19 20 21 22 23 24 25 26 52 51 50 49 48 47 46 45 44 43 42 41 40 * signals shown in bold italic are not available on the 48 pin package pp4/kwp4/pw4 pp5/kwp5/pw5 vddx vssx pm0/rxcan pm1/txcan pm2/miso pm3/ ss pm4/mosi pm5/sck ps1/txd ps0/rxd vssa vrh vdda pad07/an07 pad06/an06 pad05/an05 pad04/an04 pad03/an03 pad02/an02 pad01/an01 pad00/an00 pa 2 pa 1 pa 0 xclks/pe7 eclk/pe4 vssr vddr reset vddpll xfc vsspll extal xtal test/vpp irq/pe1 xirq/pe0 pw3/kwp3/pp3 pw0/ioc0/pt0 pw1/ioc1/pt1 pw2/ioc2/pt2 pw3/ioc3/pt3 vdd1 vss1 pw4/ioc4/pt4 ioc5/pt5 ioc6/pt6 ioc7/pt7 modc/bkgd pb4 device user guide 9s12c128dgv1/d v01.05 54 figure 2-3 pin assignments in 48 lqfp for mc9s12c-family mc9s12c-family mc9s12gc-family 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 pp5/kwp5/pw5 vddx vssx pm0/rxcan pm1/txcan pm2/miso pm3/ ss pm4/mosi pm5/sck ps1/txd ps0/rxd vssa pw0/ioc0/pt0 pw1/ioc1/pt1 pw2/ioc2/pt2 pw3/ioc3/pt3 vdd1 vss1 pw4/ioc4/pt4 ioc5/pt5 ioc6/pt6 ioc7/pt7 modc/bkgd pb4 xclks/pe7 eclk/pe4 vssr vddr reset vddpll xfc vsspll extal xtal test/vpp irq/pe1 vrh vdda pad07/an07 pad06/an06 pad05/an05 pad04/an04 pad03/an03 pad02/an02 pad01/an01 pad00/an00 pa 0 xirq/pe0 device user guide 9s12c128dgv1/d v01.05 55 2.2 signal properties summary table 2-1 signal properties pin name function 1 pin name function 2 pin name function 3 power domain internal pull resistor description ctrl reset state extal vddpll na na oscillator pins xtal vddpll na na reset vddx none none external reset pin xfc vddpll na na pll loop ?lter pin test vpp vssx na na test pin only bkgd modc t a ghi vddx up up background debug, mode pin, tag signal high pe7 noacc xclks vddx pucr up port e i/o pin, access, clock select pe6 ipipe1 modb vddx while reset pin is low: down port e i/o pin and pipe status pe5 ipipe0 moda vddx while reset pin is low: down port e i/o pin and pipe status pe4 eclk vddx pucr mode dep 1 port e i/o pin, bus clock output pe3 lstrb t a glo vddx pucr mode dep (1) port e i/o pin, low strobe, tag signal low pe2 r/ w vddx pucr mode dep (1) port e i/o pin, r/ w in expanded modes pe1 irq vddx pucr up port e input, external interrupt pin pe0 xirq vddx pucr up port e input, non-maskable interrupt pin pa[7:3] addr[15:1/ data[15:1] vddx pucr disabled port a i/o pin & multiplexed address/data pa[2:1] addr[10:9/ data[10:9] vddx pucr disabled port a i/o pin & multiplexed address/data pa[0] addr[8]/ data[8] vddx pucr disabled port a i/o pin & multiplexed address/data pb[7:5] addr[7:5]/ data[7:5] vddx pucr disabled port b i/o pin & multiplexed address/data pb[4] addr[4]/ data[4] vddx pucr disabled port b i/o pin & multiplexed address/data pb[3:0] addr[3:0]/ data[3:0] vddx pucr disabled port b i/o pin & multiplexed address/data pad[7:0] an[7:0] vdda perad/p psad disabled port ad i/o pins and atd inputs pp[7] kwp[7] vddx perp/ ppsp disabled port p i/o pins and keypad wake-up pp[6] kwp[6] romctl vddx perp/ ppsp disabled port p i/o pins, keypad wake-up and romon enable. pp[5] kwp[5] pw5 vddx perp/ ppsp disabled port p i/o pin, keypad wake-up, pw5 output pp[4:3] kwp[4:3] pw[4:3] vddx perp/ ppsp disabled port p i/o pin, keypad wake-up, pwm output device user guide 9s12c128dgv1/d v01.05 56 2.2.1 pin initialization for 48 & 52 pin lqfp bond-out versions not bonded pins if the port pins are not bonded out in the chosen package the user should initialize the registers to be inputs with enabled pull resistance to avoid excess current consumption. this applies to the following pins: (48lqfp): port a[7:1], port b[7:5], port b[3:0], porte[6,5,3,2], port p[7:6], portp[4:0], port j[7:6], ports[3:2] (52lqfp): port a[7:3], port b[7:5], port b[3:0], porte[6,5,3,2], port p[7:6], portp[2:0], port j[7:6], ports[3:2] pp[2:0] kwp[2:0] pw[2:0] vddx perp/ ppsp disabled port p i/o pins, keypad wake-up, pwm outputs pj[7:6] kwj[7:6] vddx perj/ ppsj disabled port j i/o pins and keypad wake-up pm5 sck vddx perm/ ppsm up port m i/o pin and spi sck signal pm4 mosi vddx perm/ ppsm up port m i/o pin and spi mosi signal pm3 ss vddx perm/ ppsm up port m i/o pin and spi ss signal pm2 miso vddx perm/ ppsm up port m i/o pin and spi miso signal pm1 txcan vddx perm/ ppsm up port m i/o pin and can transmit signal 2 pm0 rxcan vddx perm/ ppsm up port m i/o pin and can receive signal 2 ps[3:2] vddx pers/ ppss up port s i/o pins ps1 txd vddx pers/ ppss up port s i/o pin and sci transmit signal ps0 rxd vddx pers/ ppss up port s i/o pin and sci receive signal pt[7:5] ioc[7:5] vddx pert/ ppst disabled port t i/o pins shared with timer (tim) pt[4:0] ioc[4:0] pw[4:0] vddx pert/ ppst disabled port t i/o pins shared with timer and pwm notes : 1. the porte output buffer enable signal control at reset is determined by the pear register and is mode dependent. e.g. in special test mode rdwe=lstre=1 which enables the pe[3:2] output buffers and disables the pull-ups. refer to s12_mebi user guide for pear register details. 2. can functionality is not available on the mc9s12gc-family members pin name function 1 pin name function 2 pin name function 3 power domain internal pull resistor description ctrl reset state device user guide 9s12c128dgv1/d v01.05 57 2.3 detailed signal descriptions 2.3.1 extal, xtal oscillator pins extal and xtal are the crystal driver and external clock pins. on reset all the device clocks are derived from the extal input frequency. xtal is the crystal output. 2.3.2 reset external reset pin reset is an active low bidirectional control signal that acts as an input to initialize the mcu to a known start-up state. it also acts as an open-drain output to indicate that an internal failure has been detected in either the clock monitor or cop watchdog circuit. external circuitry connected to the reset pin should not include a large capacitance that would interfere with the ability of this signal to rise to a valid logic one within 32 eclk cycles after the low drive is released. upon detection of any reset, an internal circuit drives the reset pin low and a clocked reset sequence controls when the mcu can begin normal processing. 2.3.3 test / vpp test pin this pin is reserved for test and must be tied to vss in all applications. 2.3.4 xfc pll loop filter pin dedicated pin used to create the pll loop filter. see crg bug for more detailed information.pll loop filter. please ask your motorola representative for the interactive application note to compute pll loop filter elements. any current leakage on this pin must be avoided. figure 2-4 pll loop filter connections mcu xfc r 0 c s c p vddpll vddpll device user guide 9s12c128dgv1/d v01.05 58 2.3.5 bkgd / taghi / modc background debug, tag high & mode pin the bkgd / taghi / modc pin is used as a pseudo-open-drain pin for the background debug communication. in mcu expanded modes of operation when instruction tagging is on, an input low on this pin during the falling edge of e-clock tags the high half of the instruction word being read into the instruction queue. it is also used as a mcu operating mode select pin at the rising edge during reset, when the state of this pin is latched to the modc bit. 2.3.6 pa[7:0] / addr[15:8] / data[15:8] port a i/o pins pa7-pa0 are general purpose input or output pins,. in mcu expanded modes of operation, these pins are used for the multiplexed external address and data bus. pa[7:1] pins are not available in the 48 package version. pa[7:3] are not available in the 52 pin package version. 2.3.7 pb[7:0] / addr[7:0] / data[7:0] port b i/o pins pb7-pb0 are general purpose input or output pins. in mcu expanded modes of operation, these pins are used for the multiplexed external address and data bus. pb[7:5] and pb[3:0] pins are not available in the 48 nor 52 pin package version. 2.3.8 pe7 / noacc / xclks port e i/o pin 7 pe7 is a general purpose input or output pin. during mcu expanded modes of operation, the noacc signal, when enabled, is used to indicate that the current bus cycle is an unused or free cycle. this signal will assert when the cpu is not using the bus.the xclks is an input signal which controls whether a crystal in combination with the internal colpitts (low power) oscillator is used or whether pierce oscillator/external clock circuitry is used. the state of this pin is latched at the rising edge of reset. if the input is a logic low the extal pin is configured for an external clock drive or a pierce oscillator. if input is a logic high a colpitts oscillator circuit is configured on extal and xtal. since this pin is an input with a pull-up device during reset, if the pin is left floating, the default configuration is a colpitts oscillator circuit on extal and xtal. device user guide 9s12c128dgv1/d v01.05 59 figure 2-5 colpitts oscillator connections (pe7=1) figure 2-6 pierce oscillator connections (pe7=0) figure 2-7 external clock connections (pe7=0) mcu c 2 extal xtal crystal or vsspll ceramic resonator c 1 c dc * * due to the nature of a translated ground colpitts oscillator a dc voltage bias is applied to the crystal .please contact the crystal manufacturer for crystal dc mcu extal xtal r s * r b vsspll crystal or ceramic resonator c 2 c 1 * rs can be zero (shorted) when use with higher frequency crystals. refer to manufacturers data. mcu extal xtal cmos-compatible external oscillato r not connected (vddpll-level) device user guide 9s12c128dgv1/d v01.05 60 2.3.9 pe6 / modb / ipipe1 port e i/o pin 6 pe6 is a general purpose input or output pin. it is used as a mcu operating mode select pin during reset. the state of this pin is latched to the modb bit at the rising edge of reset. this pin is shared with the instruction queue tracking signal ipipe1}. this pin is an input with a pull-down device which is only active when reset is low. pe[6] is not available in the 48 / 52 pin package versions. 2.3.10 pe5 / moda / ipipe0 port e i/o pin 5 pe5 is a general purpose input or output pin. it is used as a mcu operating mode select pin during reset. the state of this pin is latched to the moda bit at the rising edge of reset. this pin is shared with the instruction queue tracking signal ipipe0}. this pin is an input with a pull-down device which is only active when reset is low. this pin is not available in the 48 / 52 pin package versions. 2.3.11 pe4 / eclk port e i/o pin [4] / e-clock output eclk is the output connection for the internal bus clock. it is used to demultiplex the address and data in expanded modes and is used as a timing reference. eclk frequency is equal to 1/2 the crystal frequency out of reset. the eclk pin is initially configured as eclk output with stretch in all expanded modes. the e clock output function depends upon the settings of the neclk bit in the pear register, the ivis bit in the mode register and the estr bit in the ebictl register. all clocks, including the e clock, are halted when the mcu is in stop mode. it is possible to configure the mcu to interface to slow external memory. eclk can be stretched for such accesses. reference the misc register (exstr[1:0] bits) for more information. in normal expanded narrow mode, the e clock is available for use in external select decode logic or as a constant speed clock for use in the external application system. alternatively pe4 can be used as a general purpose input or output pin. 2.3.12 pe3 / lstrb port e i/o pin [3] / low-byte strobe ( lstrb) in all modes this pin can be used as a general-purpose i/o and is an input with an active pull-up out of reset. if the strobe function is required, it should be enabled by setting the lstre bit in the pear register. this signal is used in write operations. therefore external low byte writes will not be possible until this function is enabled. this pin is also used as t a glo in special expanded modes and is multiplexed with the lstrb function. this pin is not available in the 48 / 52 pin package versions. 2.3.13 pe2 / r / w port e i/o pin [2] / read/ write in all modes this pin can be used as a general-purpose i/o and is an input with an active pull-up out of reset. if the read/write function is required it should be enabled by setting the rdwe bit in the pear register. external writes will not be possible until enabled. this pin is not available in the 48 / 52 pin package versions. device user guide 9s12c128dgv1/d v01.05 61 2.3.14 pe1 / irq port e input pin [1] / maskable interrupt pin the irq input provides a means of applying asynchronous interrupt requests to the mcu. either falling edge-sensitive triggering or level-sensitive triggering is program selectable (intcr register). irq is always enabled and configured to level-sensitive triggering out of reset. it can be disabled by clearing irqen bit (intcr register). when the mcu is reset the irq function is masked in the condition code register. this pin is always an input and can always be read. there is an active pull-up on this pin while in reset and immediately out of reset. the pull-up can be turned off by clearing pupee in the pucr register. 2.3.15 pe0 / xirq port e input pin [0] / non maskable interrupt pin the xirq input provides a means of requesting a non maskable interrupt after reset initialization. during reset, the x bit in the condition code register (ccr) is set and any interrupt is masked until mcu software enables it. because the xirq input is level sensitive, it can be connected to a multiple-source wired-or network. this pin is always an input and can always be read. there is an active pull-up on this pin while in reset and immediately out of reset. the pull-up can be turned off by clearing pupee in the pucr register. 2.3.16 pad[7:0] / an[7:0] port ad i/o pins [7:0] pad7-pad0 are general purpose i/o pins and also analog inputs for the analog to digital converter. in order to use a pad pin as a standard i/o, the corresponding atddien register bit must be set. these bits are cleared out of reset to configure the pad pins for a/d operation. when the a/d converter is active in multi-channel mode, port inputs are scanned and converted irrespective of portad configuration. thus portad pins that are configured as digital inputs or digital outputs are also converted in the a/d conversion sequence. 2.3.17 pp[7] / kwp[7] port p i/o pin [7] pp7 is a general purpose input or output pin, shared with the keypad interrupt function. when configured as an input, it can generate interrupts causing the mcu to exit stop or wait mode. this pin is not available in the 48 / 52 pin package versions. 2.3.18 pp[6] / kwp[6]/romctl port p i/o pin [6] pp6 is a general purpose input or output pin, shared with the keypad interrupt function. when configured as an input, it can generate interrupts causing the mcu to exit stop or wait mode. this pin is not available in the 48 / 52 pin package versions. during mcu expanded modes of operation, this pin is used to enable the flash eeprom memory in the memory map (romctl). at the rising edge of reset, the state of this pin is latched to the romon bit. pp6=1 in emulation modes equates to romon =0 (rom space externally mapped) pp6=0 in expanded modes equates to romon =0 (rom space externally mapped) device user guide 9s12c128dgv1/d v01.05 62 2.3.19 pp[5:0] / kwp[5:0] / pw[5:0] port p i/o pins [5:0] pp[5:0] are general purpose input or output pins, shared with the keypad interrupt function. when configured as inputs, they can generate interrupts causing the mcu to exit stop or wait mode. pp[5:0] are also shared with the pwm output signals, pw[5:0]. pins pp[2:0] are only available in the 80 pin package version. pins pp[4:3] are not available in the 48 pin package version. 2.3.20 pj[7:6] / kwj[7:6] port j i/o pins [7:6] pj[7:6] are general purpose input or output pins, shared with the keypad interrupt function. when configured as inputs, they can generate interrupts causing the mcu to exit stop or wait mode. these pins are not available in the 48 pin package version nor in the 52 pin package version. 2.3.21 pm5 / sck port m i/o pin 5 pm5 is a general purpose input or output pin and also the serial clock pin sck for the serial peripheral interface (spi). 2.3.22 pm4 / mosi port m i/o pin 4 pm4 is a general purpose input or output pin and also the master output (during master mode) or slave input (during slave mode) pin for the serial peripheral interface (spi). 2.3.23 pm3 / ss port m i/o pin 3 pm3 is a general purpose input or output pin and also the slave select pin ss for the serial peripheral interface (spi). 2.3.24 pm2 / miso port m i/o pin 2 pm2 is a general purpose input or output pin and also the master input (during master mode) or slave output (during slave mode) pin for the serial peripheral interface (spi). 2.3.25 pm1 / txcan port m i/o pin 1 pm1 is a general purpose input or output pin and the transmit pin, txcan, of the can module if available. 2.3.26 pm0 / rxcan port m i/o pin 0 pm0 is a general purpose input or output pin and the receive pin, rxcan, of the can module if available. device user guide 9s12c128dgv1/d v01.05 63 2.3.27 ps[3:2] port s i/o pins [3:2] ps3 and ps2 are general purpose input or output pins. these pins are not available in the 48 / 52 pin package versions. 2.3.28 ps1 / txd port s i/o pin 1 ps1 is a general purpose input or output pin and the transmit pin, txd, of serial communication interface (sci). 2.3.29 ps0 / rxd port s i/o pin 0 ps0 is a general purpose input or output pin and the receive pin, rxd, of serial communication interface (sci). 2.3.30 ppt[7:5] / ioc[7:5] port t i/o pins [7:5] pt7-pt5 are general purpose input or output pins. they can also be configured as the timer system input capture or output compare pins ioc7-ioc5. 2.3.31 pt[4:0] / ioc[4:0] / pw[4:0] port t i/o pins [4:0] pt4-pt0 are general purpose input or output pins. they can also be configured as the timer system input capture or output compare pins ioc4-ioc0 or as the pwm outputs pw[4:0]. 2.4 power supply pins 2.4.1 vddx,vssx power & ground pins for i/o drivers external power and ground for i/o drivers. bypass requirements depend on how heavily the mcu pins are loaded. 2.4.2 vddr, vssr power & ground pins for i/o drivers & for internal voltage regulator external power and ground for the internal voltage regulator. connecting vddr to ground disables the internal voltage regulator. 2.4.3 vdd1, vdd2, vss1, vss2 internal logic power pins power is supplied to the mcu through vdd and vss. this 2.5v supply is derived from the internal voltage regulator. there is no static load on those pins allowed. the internal voltage regulator is turned off, if vddr is tied to ground. device user guide 9s12c128dgv1/d v01.05 64 2.4.4 vdda, vssa power supply pins for atd and vreg vdda, vssa are the power supply and ground input pins for the voltage regulator reference and the analog to digital converter. 2.4.5 vrh, vrl atd reference voltage input pins vrh and vrl are the reference voltage input pins for the analog to digital converter. 2.4.6 vddpll, vsspll power supply pins for pll provides operating voltage and ground for the oscillator and the phased-locked loop. this allows the supply voltage to the oscillator and pll to be bypassed independently. this 2.5v voltage is generated by the internal voltage regulator. table 2-2 mc9s12c-family power and ground connection summary note: all vss pins must be connected together in the application. because fast signal transitions place high, short-duration current demands on the power supply, use bypass capacitors with high-frequency characteristics and place them as close to the mcu as possible. bypass requirements depend on mcu pin load. section 3 system clock description mnemonic nominal voltage description vdd1 vdd2 2.5 v internal power and ground generated by internal regulator. these also allow an external source to supply the core vdd/vss voltages and bypass the internal voltage regulator. in the 48 and 52 lqfp packages vdd2 and vss2 are not available. vss1 vss2 0v vddr 5.0 v external power and ground, supply to internal voltage regulator. vssr 0 v vddx 5.0 v external power and ground, supply to pin drivers. vssx 0 v vdda 5.0 v operating voltage and ground for the analog-to-digital converters and the reference for the internal voltage regulator, allows the supply voltage to the a/d to be bypassed independently. vssa 0 v vrh 5.0 v reference voltage low for the atd converter. in the 48 and 52 lqfp packages vrl is bonded to vssa. vrl 0 v vddpll 2.5 v provides operating voltage and ground for the phased-locked loop. this allows the supply voltage to the pll to be bypassed independently. internal power and ground generated by internal regulator. vsspll 0 v device user guide 9s12c128dgv1/d v01.05 65 the clock and reset generator provides the internal clock signals for the core and all peripheral modules. figure 3-1 shows the clock connections from the crg to all modules. consult the crg block user guide for details on clock generation. figure 3-1 clock connections section 4 modes of operation 4.1 overview eight possible modes determine the operating configuration of the mc9s12c family. each mode has an associated default memory map and external bus configuration controlled by a further pin. three low power modes exist for the device. 4.2 chip configuration summary the operating mode out of reset is determined by the states of the modc, modb, and moda pins during reset. the modc, modb, and moda bits in the mode register show the current operating mode and provide limited mode switching during operation. the states of the modc, modb, and moda pins are crg bus clock core clock extal xtal oscillator clock s12_core vreg ram sci atd flash tim tpm spi mscan pim not on 9s12gc device user guide 9s12c128dgv1/d v01.05 66 latched into these bits on the rising edge of the reset signal. the romctl signal allows the setting of the romon bit in the misc register thus controlling whether the internal flash is visible in the memory map. romo n = 1 mean the flash is visible in the memory map. the state of the romctl pin is latched into the romon bit in the misc register on the rising edge of the reset signal. for further explanation on the modes refer to the s12_mebi block guide. 4.3 security the device will make available a security feature preventing the unauthorized read and write of the memory contents. this feature allows: ? protection of the contents of flash, ? operation in single-chip mode, ? operation from external memory with internal flash disabled. the user must be reminded that part of the security must lie with the users code. an extreme example would be users code that dumps the contents of the internal program. this code would defeat the purpose of security. at the same time the user may also wish to put a back door in the users program. an example table 4-1 mode selection bkgd = modc pe6 = modb pe5 = moda pp6 = romctl romon bit mode description 000x1 special single chip, bdm allowed and active. bdm is allowed in all other modes but a serial command is required to make bdm active. 001 01 emulation expanded narrow, bdm allowed 10 0 1 0 x 0 special test (expanded wide), bdm allowed 011 01 emulation expanded wide, bdm allowed 10 1 0 0 x 1 normal single chip, bdm allowed 101 00 normal expanded narrow, bdm allowed 11 110x1 peripheral; bdm allowed but bus operations would cause bus con?icts (must not be used) 111 00 normal expanded wide, bdm allowed 11 table 4-2 clock selection based on pe7 pe7 = xclks description 1 colpitts oscillator selected 0 pierce oscillator/external clock selected device user guide 9s12c128dgv1/d v01.05 67 of this is the user downloads a key through the sci which allows access to a programming routine that updates parameters. 4.3.1 securing the microcontroller once the user has programmed the flash, the part can be secured by programming the security bits located in the flash module. these non-volatile bits will keep the part secured through resetting the part and through powering down the part. the security byte resides in a portion of the flash array. check the flash block user guide for more details on the security configuration. 4.3.2 operation of the secured microcontroller 4.3.2.1 normal single chip mode this will be the most common usage of the secured part. everything will appear the same as if the part was not secured with the exception of bdm operation. the bdm operation will be blocked. 4.3.2.2 executing from external memory the user may wish to execute from external space with a secured microcontroller. this is accomplished by resetting directly into expanded mode. the internal flash will be disabled. bdm operations will be blocked. 4.3.3 unsecuring the microcontroller in order to unsecure the microcontroller, the internal flash must be erased. this can be done through an external program in expanded mode or via a sequence of bdm commands. unsecuring is also possible via the backdoor key access. refer to flash block guide for details. once the user has erased the flash, the part can be reset into special single chip mode. this invokes a program that verifies the erasure of the internal flash. once this program completes, the user can erase and program the flash security bits to the unsecured state. this is generally done through the bdm, but the user could also change to expanded mode (by writing the mode bits through the bdm) and jumping to an external program (again through bdm commands). note that if the part goes through a reset before the security bits are reprogrammed to the unsecure state, the part will be secured again. 4.4 low power modes the microcontroller features three main low power modes. consult the respective block user guide for information on the module behavior in stop, pseudo stop, and wait mode. an important source of information about the clock system is the clock and reset generator user guide (crg). device user guide 9s12c128dgv1/d v01.05 68 4.4.1 stop executing the cpu stop instruction stops all clocks and the oscillator thus putting the chip in fully static mode. wake up from this mode can be done via reset or external interrupts. 4.4.2 pseudo stop this mode is entered by executing the cpu stop instruction. in this mode the oscillator is still running and the real time interrupt (rti) or watchdog (cop) sub module can stay active. other peripherals are turned off. this mode consumes more current than the full stop mode, but the wake up time from this mode is significantly shorter. 4.4.3 wait this mode is entered by executing the cpu wai instruction. in this mode the cpu will not execute instructions. the internal cpu signals (address and databus) will be fully static. all peripherals stay active. for further power consumption reduction the peripherals can individually turn off their local clocks. 4.4.4 run although this is not a low power mode, unused peripheral modules should not be enabled in order to save power. section 5 resets and interrupts 5.1 overview consult the exception processing section of the cpu12 reference manual for information. 5.2 vectors 5.2.1 vector table table 5-1 lists interrupt sources and vectors in default order of priority. table 5-1 interrupt vector locations vector address interrupt source ccr mask local enable hprio value to elevate $fffe, $ffff external reset, power on reset or low voltage reset (see crg flags register to determine reset source) none none C $fffc, $fffd clock monitor fail reset none copctl (cme, fcme) C $fffa, $fffb cop failure reset none cop rate select C $fff8, $fff9 unimplemented instruction trap none none C device user guide 9s12c128dgv1/d v01.05 69 5.3 resets resets are a subset of the interrupts featured in table 5-1 . the different sources capable of generating a system reset are summarized in table 5-2 . when a reset occurs, mcu registers and control bits are $fff6, $fff7 swi none none C $fff4, $fff5 xirq x-bit none C $fff2, $fff3 irq i-bit intcr (irqen) $f2 $fff0, $fff1 real time interrupt i-bit crgint (rtie) $f0 $ffee, $ffef standard timer channel 0 i-bit tie (c0i) $ee $ffec, $ffed standard timer channel 1 i-bit tie (c1i) $ec $ffea, $ffeb standard timer channel 2 i-bit tie (c2i) $ea $ffe8, $ffe9 standard timer channel 3 i-bit tie (c3i) $e8 $ffe6, $ffe7 standard timer channel 4 i-bit tie (c4i) $e6 $ffe4, $ffe5 standard timer channel 5 i-bit tie (c5i) $e4 $ffe2, $ffe3 standard timer channel 6 i-bit tie (c6i) $e2 $ffe0, $ffe1 standard timer channel 7 i-bit tie (c7i) $e0 $ffde, $ffdf standard timer over?ow i-bit tmsk2 (toi) $de $ffdc, $ffdd pulse accumulator a over?ow i-bit pactl (paovi) $dc $ffda, $ffdb pulse accumulator input edge i-bit pactl (pai) $da $ffd8, $ffd9 spi i-bit spicr1 (spie, sptie) $d8 $ffd6, $ffd7 sci i-bit scicr2 (tie, tcie, rie, ilie) $d6 $ffd4, $ffd5 reserved $ffd2, $ffd3 atd i-bit atdctl2 (ascie) $d2 $ffd0, $ffd1 reserved $ffce, $ffcf port j i-bit piep (piep7-6) $ce $ffcc, $ffcd reserved $ffca, $ffcb reserved $ffc8, $ffc9 reserved $ffc6, $ffc7 crg pll lock i-bit pllcr (lockie) $c6 $ffc4, $ffc5 crg self clock mode i-bit pllcr (scmie) $c4 $ffba to $ffc3 reserved $ffb8, $ffb9 flash i-bit fcnfg (ccie, cbeie) $b8 $ffb6, $ffb7 can wake-up 1 i-bit canrier (wupie) $b6 $ffb4, $ffb5 can errors 1 i-bit canrier (cscie, ovrie) $b4 $ffb2, $ffb3 can receive 1 i-bit canrier (rxfie) $b2 $ffb0, $ffb1 can transmit 1 i-bit cantier (txeie[2:0]) $b0 $ff90 to $ffaf reserved $ff8e, $ff8f port p i-bit piep (piep7-0) $8e $ff8c, $ff8d pwm emergency shutdown i-bit pwmsdn(pwmie) $8c $ff8a, $ff8b vreg lvi i-bit ctrl0 (lvie) $8a $ff80 to $ff89 reserved notes : 1. not available on mc9s12gc-family members device user guide 9s12c128dgv1/d v01.05 70 changed to known start-up states. refer to the respective module block user guides for register reset states. 5.3.1 reset summary table 5.3.2 effects of reset when a reset occurs, mcu registers and control bits are changed to known start-up states. refer to the respective module block user guides for register reset states. refer to the hcs12 multiplexed external bus interface (mebi) block guide for mode dependent pin configuration of port a, b and e out of reset. refer to the pim block user guide for reset configurations of all peripheral module ports. refer to figure 1-2 to figure 1-5 footnotes for locations of the memories depending on the operating mode after reset. the ram array is not automatically initialized out of reset. note: for devices assembled in 48-pin or 52-pin lqfp packages all non-bonded out pins should be configured as outputs after reset in order to avoid current drawn from floating inputs. refer to table 2-1 for affected pins. section 6 hcs12 core block description consult the individual block guides for information about the hcs12 core modules, i.e. central processing unit (cpu), interrupt module (int), module mapping control module (mmc), multiplexed external bus interface (mebi), debug12 module (dbg12) and background debug mode module (bdm). where the cpu12 reference manual refers to cycles this is equivalent to device bus clock periods. 6.1 device-specific information 6.1.1 ppage external paging is not supported on these devices. in order to access the 16k flash blocks in the address range $8000-$bfff the ppage register must be loaded with the corresponding value for this range. refer to table 6-1 for device specific page mapping. table 5-2 reset summary reset priority source vector power-on reset 1 crg module $fffe, $ffff external reset 1 reset pin $fffe, $ffff low voltage reset 1 vreg module $fffe, $ffff clock monitor reset 2 crg module $fffc, $fffd cop watchdog reset 3 crg module $fffa, $fffb device user guide 9s12c128dgv1/d v01.05 71 for all devices flash page 3f is visible in the $c000-$ffff range if romon is set. for all devices (ecept 9s12gc16) page 3e is also visible in the $4000-$7fff range if romhm is cleared and romon is set. for all devices apart from mc9s12c32 flash page 3d is visible in the $0000-$3fff range if romon is set... table 6-1 device specific flash page mapping 6.1.2 bdm alternate clock the bdm section of s12 core user guide reference to alternate clock is equivalent to oscillator clock. 6.1.3 extended address range emulation implications in order to emulate the mc9s12gc or mc9s12c-family devices, external addressing of a 128k memory map is required. this is provided in a 112 lqfp package version which includes the 3 necessary extra external address bus signals via portk[2:0]. this package version is for emulation only and not provided as a general production package. the reset state of ddrk is $00, configuring the pins as inputs. the reset state of pupke in the pucr register is 1 enabling the internal portk pullups. in this reset state the pull-ups provide a defined state and prevent a floating input, thereby preventing unnecessary current flow at the input stage. device page page visible with ppage contents mc9s12gc16 3f $00,$01,$02,$03,$04,$05,$06,$07,$08,$09......$36,$37,$38,$39,$3a,$3b,$3c,$3d,$3e,$3f mc9s12c32 mc9s12gc32 3e $00,$02,$04,$06,$08,$0a,$0c,$0e,$10,$12......$2c,$2e,$30,$32,$34,$36,$38,$3a,$3c,$3e 3f $01,$03,$05,$07,$09,$0b,$0d,$0f,$11,$13.....$2d,$2f,$31,$33,$35,$37,$39,$3b,$3d,$3f mc9s12c64 mc9s12gc64 3c $00,$04,$08,$0c,$10,$14,$18,$1c,$20,$24,$28,$2c,$30,$34,$38,$3c 3d $01,$05,$09,$0d,$11,$15,$19,$1d,$21,$25,$29,$2d,$31,$35,$39,$3d 3e $02,$06,$0a,$0e,$12,$16,$1a,$1e,$22,$26,$2a,$2e,$32,$36,$3a,$3e 3f $03,$07,$0b,$0f,$13,$17,$1b,$1f,$23,$27,$2b,$2f,$33,$37,$3b,$3f mc9s12c96 3a $00,$02,$08,$0a,$10,$12,$18,$1a,$20,$22,$28,$2a,$30,$32,$38,$3a 3b $01,$03,$09,$0b,$11,$13,$19,$1b,$21,$23,$29,$2b,$31,$33,$39,$3b 3c $04,$0c,$14,$1c,$24,$2c,$34,$3c 3d $05,$0d,$15,$1d,$25,$2d,$35,$3d 3e $06,$0e,$16,$1e,$26,$2e,$36,$3e 3f $07,$0f,$17,$1f,$27,$2f,$37,$3f mc9s12c128 mc9s12gc128 38 $00,$08,$10,$18,$20,$28,$30,$38 39 $01,$09,$11,$19,$21,$29,$31,$39 3a $02,$0a,$12,$1a,$22,$2a,$32,$3a 3b $03,$0b,$13,$1b,$23,$2b,$33,$3b 3c $04,$0c,$14,$1c,$24,$2c,$34,$3c 3d $05,$0d,$15,$1d,$25,$2d,$35,$3d 3e $06,$0e,$16,$1e,$26,$2e,$36,$3e 3f $07,$0f,$17,$1f,$27,$2f,$37,$3f device user guide 9s12c128dgv1/d v01.05 72 to prevent unnecessary current flow in production package options, the states of ddrk and pupke should not be changed by software. section 7 voltage regulator (vreg) block description consult the vreg block user guide for information about the dual output linear voltage regulator. 7.1 device-specific information the vreg is part of the ipbus domain. 7.1.1 vregen vregen is connected internally to vddr. 7.1.2 vdd1, vdd2, vss1, vss2 in the 80 pin qfp package versions, both internal vdd and vss of the 2.5v domain are bonded out on 2 sides of the device as two pin pairs (vdd1, vss1 & vdd2, vss2). vdd1 and vdd2 are connected together internally. vss1 and vss2 are connected together internally. the extra pin pair enables systems using the 80 pin package to employ better supply routing and further decoupling. section 8 recommended printed circuit board layout the pcb must be carefully laid out to ensure proper operation of the voltage regulator as well as of the mcu itself. the following rules must be observed: ? every supply pair must be decoupled by a ceramic capacitor connected as near as possible to the corresponding pins (c1 - c6). ? central point of the ground star should be the vssr pin. ? use low ohmic low inductance connections between vss1, vss2 and vssr. ? vsspll must be directly connected to vssr. ? keep traces of vsspll, extal and xtal as short as possible and occupied board area for c7, c8, c11 and q1 as small as possible. ? do not place other signals or supplies underneath area occupied by c7, c8, c10 and q1 and the connection area to the mcu. ? central power input should be fed in at the vdda/vssa pins. device user guide 9s12c128dgv1/d v01.05 73 table 8-1 recommended external component values component purpose type value c1 vdd1 ?lter capapcitor ceramic x7r 220nf, 470nf 1 notes : 1. in 48lqfp and 52lqfp package versions, vdd2 is not available. thus 470nf must be connected to vdd1. c2 vdd2 ?lter capacitor (80 qfp only) ceramic x7r 220nf c3 vdda ?lter capacitor ceramic x7r 100nf c4 vddr ?lter capacitor x7r/tantalum >=100nf c5 vddpll ?lter capacitor ceramic x7r 100nf c6 vddx ?lter capacitor x7r/tantalum >=100nf c7 osc load capacitor see pll speci?cation chapter c8 osc load capacitor c9 pll loop ?lter capacitor see pll speci?cation chapter c10 pll loop ?lter capacitor c11 dc cutoff capacitor colpitts mode only, if recommended by quartz manufacturer r1 pll loop ?lter resistor see pll speci?cation chapter r2 / r b pll loop ?lter resistor pierce mode only r3 / r s pll loop ?lter resistor q1 quartz device user guide 9s12c128dgv1/d v01.05 74 figure 8-1 recommended pcb layout (48 lqfp) c5 c4 c1 c6 c3 c8 c7 q1 c10 c9 r1 vddx vssx vddr vssr vdd1 vss1 vddpll vsspll vdda vssa c11 oscillator in note: colpitts mode. device user guide 9s12c128dgv1/d v01.05 75 ) figure 8-2 recommended pcb layout (52 lqfp) c4 c1 c6 c8 c7 q1 c10 c9 r1 vddx vssx vddr vssr vdd1 vss1 vddpll vsspll vdda vssa c11 note: oscillator in colpitts mode. c3 c5 device user guide 9s12c128dgv1/d v01.05 76 ) figure 8-3 recommended pcb layout (80 qfp) vdda c5 c4 c8 c7 q1 c10 c9 r1 vddr vssr vddpll vsspll c11 c6 c3 vddx vssx vssa c1 vdd1 vss1 c2 vdd2 vss2 note: oscillator in colpitts mode. device user guide 9s12c128dgv1/d v01.05 77 figure 8-4 recommended pcb layout for 48 lqfp pierce oscillator c4 c1 c6 vddx vssx vddr vssr vdd1 vss1 vdda vssa c3 c5 c10 c9 r1 vsspll vddpll r2 c7 r3 c8 q1 device user guide 9s12c128dgv1/d v01.05 78 figure 8-5 recommended pcb layout for 52 lqfp pierce oscillator c4 c1 c6 vddx vssx vddr vssr vdd1 vss1 vdda vssa c3 c5 c10 c9 r1 vsspll vddpll r2 c7 r3 c8 q1 device user guide 9s12c128dgv1/d v01.05 79 figure 8-6 recommended pcb layout for 80qfp pierce oscillator section 9 clock reset generator (crg) block description consult the crg block user guide for information about the clock and reset generator module. 9.1 device-specific information the crg is part of the ipbus domain. c5 c4 c3 c2 c10 c9 r1 c6 c1 vdd1 vss1 vss2 vdd2 vssr vddr vsspll vddpll vdda vssa vssx vddx r2 c7 r3 c8 q1 vsspll device user guide 9s12c128dgv1/d v01.05 80 the low voltage reset feature uses the low voltage reset signal from the vreg module as an input to the crg module. when the regulator output voltage supply to the internal chip logic falls below a specified threshold the lvr signal from the vreg module causes the crg module to generate a reset. consult the vreg block user guide for voltage level specifications. 9.1.1 xclks the xclks input signal is active low (see 2.3.8 pe7 / noacc / xclks port e i/o pin 7 ). section 10 oscillator (osc) block description consult the osc block user guide for information about the oscillator module. section 11 timer (tim) block description consult the tim_16b8c block user guide for information about the timer module. section 12 analog to digital converter (atd) block description 12.1 device-specific information 12.1.1 vrl (voltage reference low) in the 48 and 52 pin package versions, the vrl pad is bonded internally to the vssa pin. consult the atd_10b8c block user guide for further information about the a/d converter module. section 13 serial communications interface (sci) block description consult the sci block user guide for information about the asynchronous serial communications interface module. section 14 serial peripheral interface (spi) block description consult the spi block user guide for information about the serial peripheral interface module. device user guide 9s12c128dgv1/d v01.05 81 consult the spi block user guide for information about the synchronous serial communications interface module. section 15 flash block description consult the fts16k block user guide for information about the flash module for the mc9s12gc16. consult the fts32k block user guide for information about the flash module for the mc9s12c32 or mc9s12gc32. consult the fts64k block user guide for information about the flash module for the mc9s12c64 or mc9s12gc64. consult the fts96k block user guide for information about the flash module for the mc9s12c96. consult the fts128k block user guide for information about the flash module for the mc9s12c128or mc9s12gc128. section 16 ram block description this module supports single-cycle misaligned word accesses without wait states. the mc912gc16 features a single 1k byte ram module. the mc9s12c32 and mc9s12gc32 feature a 2k byte ram module. the mc9s12c64, mc9s12gc64, mc9s12c96, mc9s12c128 and mc9s12gc128 versions feature a 4k byte ram module. section 17 pulse width modulator (pwm) block description consult the pwm_8b6c block user guide for information about the pulse width modulator module. section 18 mscan block description consult the mscan block user guide for information about the motorola scalable can module. this module is not available on the mc9gc-family members. section 19 port integration module (pim) block description device user guide 9s12c128dgv1/d v01.05 82 consult the pim_9c32 block user guide for information about the port integration module for all versions of the mc9ds12gc and mc9s12c-family. the modrr register within the pim allows for mapping of pwm channels to portt in the absence of portp pins for the low pin count packages. for the 80qfp package option it is recommended not to use modrr since this is intended to support pwm channel availability in low pin count packages. note that when mapping pwm channels to portt in an 80qfp option, the associated pwm channels are then mapped to both portp and portt. device user guide 9s12c128dgv1/d v01.05 83 appendix a electrical characteristics a.1 general note: the electrical characteristics given in this section are preliminary and should be used as a guide only. values cannot be guaranteed by motorola and are subject to change without notice. note: the parts are specified and tested over the 5v and 3.3v ranges. for the intermediate range, generally the electrical specifications for the 3.3v range apply, but the parts are not tested in production test in the intermediate range. this supplement contains the most accurate electrical information for the mc9s12c-family microcontrollers available at the time of publication. the information should be considered preliminary and is subject to change. this introduction is intended to give an overview on several common topics like power supply, current injection etc. a.1.1 parameter classification the electrical parameters shown in this supplement are guaranteed by various methods. to give the customer a better understanding the following classification is used and the parameters are tagged accordingly in the tables where appropriate. note: this classification will be added at a later release of the specification p: those parameters are guaranteed during production testing on each individual device. c: those parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations. they are regularly verified by production monitors. t: those parameters are achieved by design characterization on a small sample size from typical devices. all values shown in the typical column are within this category. d: those parameters are derived mainly from simulations. a.1.2 power supply the mc9s12c-family and mc9s12gc-family members utilize several pins to supply power to the i/o ports, a/d converter, oscillator and pll as well as the internal logic. the vdda, vssa pair supplies the a/d converter. the vddx, vssx pair supplies the i/o pins the vddr, vssr pair supplies the internal voltage regulator. vdd1, vss1, vdd2 and vss2 are the supply pins for the digital logic. vddpll, vsspll supply the oscillator and the pll. device user guide 9s12c128dgv1/d v01.05 84 vss1 and vss2 are internally connected by metal. vdd1 and vdd2 are internally connected by metal. vdda, vddx, vddr as well as vssa, vssx, vssr are connected by anti-parallel diodes for esd protection. note: in the following context vdd5 is used for either vdda, vddr and vddx; vss5 is used for either vssa, vssr and vssx unless otherwise noted. idd5 denotes the sum of the currents flowing into the vdda, vddx and vddr pins. vdd is used for vdd1, vdd2 and vddpll, vss is used for vss1, vss2 and vsspll. idd is used for the sum of the currents flowing into vdd1 and vdd2. a.1.3 pins there are four groups of functional pins. a.1.3.1 5v i/o pins those i/o pins have a nominal level of 5v. this class of pins is comprised of all port i/o pins, the analog inputs, bkgd pin and the reset inputs.the internal structure of all those pins is identical, however some of the functionality may be disabled. e.g. pull-up and pull-down resistors may be disabled permanently. a.1.3.2 analog reference this class is made up by the two vrh and vrl pins. in 48 and 52 pin package versions the vrl pad is bonded to the vssa pin. a.1.3.3 oscillator the pins xfc, extal, xtal dedicated to the oscillator have a nominal 2.5v level. they are supplied by vddpll. a.1.3.4 test this pin is used for production testing only. a.1.4 current injection power supply must maintain regulation within operating v dd5 or v dd range during instantaneous and operating maximum current conditions. if positive injection current (v in >v dd5 ) is greater than i dd5 , the injection current may flow out of vdd5 and could result in external power supply going out of regulation. insure external vdd5 load will shunt current greater than maximum injection current. this will be the greatest risk when the mcu is not consuming power; e.g. if no system clock is present, or if clock rate is very low which would reduce overall power consumption. device user guide 9s12c128dgv1/d v01.05 85 a.1.5 absolute maximum ratings absolute maximum ratings are stress ratings only. a functional operation under or outside those maxima is not guaranteed. stress beyond those limits may affect the reliability or cause permanent damage of the device. this device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either v ss5 or v dd5 ). table a-1 absolute maximum ratings num rating symbol min max unit 1 i/o, regulator and analog supply voltage v dd5 -0.3 6.5 v 2 digital logic supply voltage 1 notes : 1. the device contains an internal voltage regulator to generate the logic and pll supply out of the i/o supply. the absolute maximum ratings apply when the device is powered from an external source. v dd -0.3 3.0 v 3 pll supply voltage (1) v ddpll -0.3 3.0 v 4 voltage difference vddx to vddr and vdda d vddx -0.3 0.3 v 5 voltage difference vssx to vssr and vssa d vssx -0.3 0.3 v 6 digital i/o input voltage v in -0.3 6.5 v 7 analog reference v rh, v rl -0.3 6.5 v 8 xfc, extal, xtal inputs v ilv -0.3 3.0 v 9 test input v test -0.3 10.0 v 10 instantaneous maximum current single pin limit for all digital i/o pins 2 2. all digital i/o pins are internally clamped to v ssx and v ddx , v ssr and v ddr or v ssa and v dda . i d -25 +25 ma 11 instantaneous maximum current single pin limit for xfc, extal, xtal 3 3. these pins are internally clamped to v sspll and v ddpll i dl -25 +25 ma 12 instantaneous maximum current single pin limit for test 4 4. this pin is clamped low to v ssx , but not clamped high. this pin must be tied low in applications. i dt -0.25 0 ma 13 operating temperature range (packaged) t a C 40 125 c 14 operating temperature range (junction) t j C 40 140 c 15 storage temperature range t stg C 65 155 c device user guide 9s12c128dgv1/d v01.05 86 a.1.6 esd protection and latch-up immunity all esd testing is in conformity with cdf-aec-q100 stress test qualification for automotive grade integrated circuits. during the device qualification esd stresses were performed for the human body model (hbm), the machine model (mm) and the charge device model. a device will be defined as a failure if after exposure to esd pulses the device no longer meets the device specification. complete dc parametric and functional testing is performed per the applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification. a.1.7 operating conditions this chapter describes the operating conditions of the devices. unless otherwise noted those conditions apply to all the following data. table a-2 esd and latch-up test conditions model description symbol value unit human body series resistance r1 1500 ohm storage capacitance c 100 pf number of pulse per pin positive negative - - 3 3 machine series resistance r1 0 ohm storage capacitance c 200 pf number of pulse per pin positive negative - - 3 3 latch-up minimum input voltage limit -2.5 v maximum input voltage limit 7.5 v table a-3 esd and latch-up protection characteristics num c rating symbol min max unit 1 c human body model (hbm) v hbm 2000 - v 2 c machine model (mm) v mm 200 - v 3 c charge device model (cdm) v cdm 500 - v 4c latch-up current at 125 c positive negative i lat +100 -100 -ma 5c latch-up current at 27 c positive negative i lat +200 -200 -ma device user guide 9s12c128dgv1/d v01.05 87 note: instead of specifying ambient temperature all parameters are specified for the more meaningful silicon junction temperature. for power dissipation calculations refer to section a.1.8 power dissipation and thermal characteristics . a.1.8 power dissipation and thermal characteristics power dissipation and thermal characteristics are closely related. the user must assure that the maximum operating junction temperature is not exceeded. the average chip-junction temperature (t j )in c can be obtained from: the total power dissipation can be calculated from: table a-4 operating conditions rating symbol min typ max unit i/o, regulator and analog supply voltage v dd5 2.97 5 5.5 v digital logic supply voltage 1 notes : 1. the device contains an internal voltage regulator to generate the logic and pll supply out of the i/o supply. the absolute maximum ratings apply when this regulator is disabled and the device is powered from an external source. v dd 2.35 2.5 2.75 v pll supply voltage (1) v ddpll 2.35 2.5 2.75 v voltage difference vddx to vdda d vddx -0.1 0 0.1 v voltage difference vssx to vssr and vssa d vssx -0.1 0 0.1 v oscillator f osc 0.5 - 16 mhz bus frequency f bus 2 2. some blocks e.g. atd (conversion) and nvms (program/erase) require higher bus frequencies for proper oper- ation. 0.25 - 25 mhz operating junction temperature range t j -40 - 140 c t j t a p d q ja () + = t j junction temperature, [ c ] = t a ambient temperature, [ c ] = p d total chip power dissipation, [w] = q ja package thermal resistance, [ c/w] = p d p int p io + = p int chip internal power dissipation, [w] = device user guide 9s12c128dgv1/d v01.05 88 two cases with internal voltage regulator enabled and disabled must be considered: 1. internal voltage regulator disabled which is the sum of all output currents on i/o ports associated with vddx and vddm. for r dson is valid: respectively 2. internal voltage regulator enabled i ddr is the current shown in table a-8 and not the overall current flowing into vddr, which additionally contains the current flowing into the external loads with output high. p int i dd v dd i ddpll v ddpll i dda +v dda + = p io r dson i ? i io i 2 = r dson v ol i ol ------------ for outputs driven low ; = r dson v dd5 v oh C i oh ------------------------------------ for outputs driven high ; = p int i ddr v ddr i dda v dda + = p io r dson i ? i io i 2 = device user guide 9s12c128dgv1/d v01.05 89 which is the sum of all output currents on i/o ports associated with vddx and vddr. a.1.9 i/o characteristics this section describes the characteristics of all i/o pins. all parameters are not always applicable, e.g. not all pins feature pull up/down resistances. table a-5 thermal package characteristics 1 notes : 1. the values for thermal resistance are achieved by package simulations num c rating symbol min typ max unit 1t thermal resistance lqfp48, single layer pcb 2 2. pc board according to eia/jedec standard 51-2 q ja --69 o c/w 2t thermal resistance lqfp48, double sided pcb with 2 internal planes 3 3. pc board according to eia/jedec standard 51-7 q ja --53 o c/w 3 t junction to board lqfp48 q jb 30 o c/w 4 t junction to case lqfp48 q jc 20 o c/w 5 t junction to package top lqfp48 y jt 4 o c/w 6 t thermal resistance lqfp52, single sided pcb q ja --65 o c/w 7t thermal resistance lqfp52, double sided pcb with 2 internal planes q ja --49 o c/w 8 t junction to board lqfp52 q jb 31 o c/w 9 t junction to case lqfp52 q jc 17 o c/w 10 t junction to package top lqfp52 y jt 3 o c/w 11 t thermal resistance qfp 80, single sided pcb q ja --52 o c/w 12 t thermal resistance qfp 80, double sided pcb with 2 internal planes q ja --42 o c/w 13 t junction to board qfp80 q jb 28 o c/w 14 t junction to case qfp80 q jc 18 o c/w 15 t junction to package top qfp80 y jt 4 o c/w device user guide 9s12c128dgv1/d v01.05 90 table a-6 5v i/o characteristics conditions are 4.5< vddx <5.5v termperature from -40?c to +140?c, unless otherwise noted num c rating symbol min typ max unit 1 p input high voltage v ih 0.65*v dd5 --v t input high voltage v ih - - vdd5 + 0.3 v 2 p input low voltage v il -- 0.35*v dd5 v t input low voltage v il vss5 - 0.3 - - v 3 c input hysteresis v hys 250 mv 4p input leakage current (pins in high ohmic input mode) 1 v in = v dd5 or v ss5 notes : 1. maximum leakage current occurs at maximum operating temperature. current decreases by approximately one-half for each 8 c to 12 c in the temperature range from 50 c to 125 c. i in C1 - 1 m a 5c output high voltage (pins in output mode) partial drive i oh = C2ma v oh v dd5 C 0.8 --v 6p output high voltage (pins in output mode) full drive ioh = C10ma v oh v dd5 C 0.8 --v 7c output low voltage (pins in output mode) partial drive iol = +2ma v ol - - 0.8 v 8p output low voltage (pins in output mode) full drive i ol = +10ma v ol - - 0.8 v 9p internal pull up device current, tested at v il max. i pul - - -130 m a 10 c internal pull up device current, tested at v ih min. i puh -10 - - m a 11 p internal pull down device current, tested at v ih min. i pdh - - 130 m a 12 c internal pull down device current, tested at v il max. i pdl 10 - - m a 13 d input capacitance c in 7-pf 14 t injection current 2 single pin limit total device limit. sum of all injected currents 2. refer to section a.1.4 current injection , for more details i ics i icp -2.5 -25 - 2.5 25 ma 15 p port p, j interrupt input pulse ?ltered 3 3. parameter only applies in stop or pseudo stop mode. t pign 3 m s 16 p port p, j interrupt input pulse passed 3 t pval 10 m s device user guide 9s12c128dgv1/d v01.05 91 table a-7 3.3v i/o characteristics conditions are vddx=3.3v +/-10%, termperature from -40?c to +140?c, unless otherwise noted num c rating symbol min typ max unit 1 p input high voltage v ih 0.65*v dd5 --v t input high voltage v ih - - vdd5 + 0.3 v 2 p input low voltage v il -- 0.35*v dd5 v t input low voltage v il vss5 - 0.3 - - v 3 c input hysteresis v hys 250 mv 4p input leakage current (pins in high ohmic input mode) 1 v in = v dd5 or v ss5 notes : 1. maximum leakage current occurs at maximum operating temperature. current decreases by approximately one-half for each 8 c to 12 c in the temperature range from 50 c to 125 c. i in C1 - 1 m a 5c output high voltage (pins in output mode) partial drive i oh = C0.75ma v oh v dd5 C 0.4 --v 6p output high voltage (pins in output mode) full drive i oh = C4ma v oh v dd5 C 0.4 --v 7c output low voltage (pins in output mode) partial drive i ol = +0.9ma v ol - - 0.4 v 8p output low voltage (pins in output mode) full drive i ol = +4.75ma v ol - - 0.4 v 9p internal pull up device current, tested at v il max. i pul - - C60 m a 10 c internal pull up device current, tested at v ih min. i puh -6 - - m a 11 p internal pull down device current, tested at v ih min. i pdh --60 m a 12 c internal pull down device current, tested at v il max. i pdl 6- - m a 11 d input capacitance c in 7-pf 12 t injection current 2 single pin limit total device limit. sum of all injected currents 2. refer to section a.1.4 current injection , for more details i ics i icp -2.5 -25 - 2.5 25 ma 13 p port p, j interrupt input pulse ?ltered 3 3. parameter only applies in stop or pseudo stop mode. t pign 3 m s 14 p port p, j interrupt input pulse passed 3 t pval 10 m s device user guide 9s12c128dgv1/d v01.05 92 a.1.10 supply currents this section describes the current consumption characteristics of the device as well as the conditions for the measurements. a.1.10.1 measurement conditions all measurements are without output loads. unless otherwise noted the currents are measured in single chip mode, internal voltage regulator enabled and at 25mhz bus frequency using a 4mhz oscillator. a.1.10.2 additional remarks in expanded modes the currents flowing in the system are highly dependent on the load at the address, data and control signals as well as on the duty cycle of those signals. no generally applicable numbers can be given. a very good estimate is to take the single chip currents and add the currents due to the external loads. device user guide 9s12c128dgv1/d v01.05 93 table a-8 supply current characteristics for mc9s12c32 conditions are shown in table a-4 with internal regulator enabled unless otherwise noted num c rating symbol min typ max unit 1 p run supply current single chip i dd5 35 ma 2 p p c wait supply current all modules enabled vddr<4.9v, only rti enabled (2) vddr>4.9v, only rti enabled i ddw 3.5 2.5 30 8 ma 3 c p c p c p c p pseudo stop current (rti and cop disabled) (2)(3) -40 c 27 c 85 c "c" temp option 100?c 105 c "v" temp option 120?c 125 c "m" temp option 140 c i ddps 1 notes : 1. stop current measured in production test at increased junction temperature, hence for temp option "c" the test is carried out at 100?c although the temperature specification is 85?c. similarly for "v" and "m" options the temperature used in test lies 15?c above the temperature option specification. 340 360 500 550 590 720 780 1100 450 1450 1900 4500 m a 4 c c c c c pseudo stop current (rti and cop enabled) 23 -40 c 27 c 85 c 105 c 125 c 2. pll off 3. at those low power dissipation levels t j = t a can be assumed i ddps 1 540 700 750 880 1300 m a 5 c p c p c p c p stop current (3) -40 c 27 c 85 c "c" temp option 100?c 105 c "v" temp option 120?c 125 c "m" temp option 140 c i dds (1) 10 20 100 140 170 300 350 520 80 1000 1400 4000 m a device user guide 9s12c128dgv1/d v01.05 94 table a-9 supply current characteristics for mc9s12c64,mc9s12c96,mc9s12c128 conditions are shown in table a-4 with internal regulator enabled unless otherwise noted num c rating symbol min typ max unit 1 p run supply current single chip, i dd5 45 ma 2 p p c wait supply current all modules enabled vddr<4.9v, only rti enabled (2) vddr>4.9v, only rti enabled i ddw 2.5 3.5 33 8 ma 6 c p c p c p c p pseudo stop current (rti and cop disabled) (2)(3) -40 c 27 c 85 c "c" temp option 100?c 105 c "v" temp option 120?c 125 c "m" temp option 140 c i ddps 1 notes : 1. stop current measured in production test at increased junction temperature, hence for temp option "c" the test is carried out at 100?c although the temperature specification is 85?c. similarly for "v" and "m" options the temperature used in test lies 15?c above the temperature option specification. 190 200 300 400 450 600 650 1000 250 1400 1900 4800 m a 4 c c c c c pseudo stop current (rti and cop enabled) 23 -40 c 27 c 85 c 105 c 125 c 2. pll off 3. at those low power dissipation levels t j = t a can be assumed i ddps 1 370 500 590 780 1200 m a 5 c p c p c p c p stop current (3) -40 c 27 c 85 c "c" temp option 100?c 105 c "v" temp option 120?c 125 c "m" temp option 140 c i dds (1) 12 25 130 160 200 350 400 600 100 1200 1700 4500 m a device user guide 9s12c128dgv1/d v01.05 95 appendix b electrical specifications b.1 voltage regulator operating conditions table b-1 voltage regulator electrical parameters nu m c characteristic symbol min typical max unit 1 p input voltages v vddr, a 2.97 5.5 v 2c regulator current reduced power mode shutdown mode i reg 20 12 50 40 m a m a 3p output voltage core full performance mode v dd 2.35 2.5 2.75 v 4p low voltage interrupt 1 assert level c32, gc32 assert level c64, c96,c128 gc64, gc128 deassert level c32, gc32 deassert level c64, c96, c128 gc64, gc128 notes : 1. monitors v dda , active only in full performance mode. indicates i/o & adc performance degradation due to low supply voltage. v lvia v lvia v lvid v lvid 4.30 4.10 4.42 4.25 4.53 4.37 4.65 4.52 4.77 4.66 4.89 4.77 v v v v 5p low voltage reset 2 assert level c32, gc32 assert level c64, c96, c128 gc64, gc128 2. monitors v dd , active only in full performance mode. mcu is monitored by the por in rpm (see figure b-1 ) v lvra 2.25 2.25 2.3 2.35 v 6p low voltage reset (2) deassert level v lvrd 2.55 v 7c power-on reset 3 assert level deassert level 3. monitors v dd . active in all modes. note: the electrical characteristics given in this section are preliminary and should be used as a guide only. values in this section cannot be guaranteed by motorola and are subject to change without notice. v pora v pord 0.97 2.05 v v device user guide 9s12c128dgv1/d v01.05 96 b.2 chip power-up and lvi/lvr graphical explanation voltage regulator sub modules lvi (low voltage interrupt), por (power-on reset) and lvr (low voltage reset) handle chip power-up or drops of the supply voltage. their function is described in figure b-1 . figure b-1 voltage regulator - chip power-up and voltage drops (not scaled) b.3 output loads b.3.1 resistive loads the on-chip voltage regulator is intended to supply the internal logic and oscillator circuits allows no external dc loads. v lvid v lvia v lvrd v lvra v pord lvi por lvr t v v dda v dd lvi enabled lvi disabled due to lvr device user guide 9s12c128dgv1/d v01.05 97 b.3.2 capacitive loads the capacitive loads are specified in table b-2 . ceramic capacitors with x7r dielectricum are required. table b-2 voltage regulator - capacitive loads num characteristic symbol min typical max unit 1 vdd external capacitive load c ddext 400 440 12000 nf 2 vddpll external capacitive load c ddpllext 90 220 5000 nf device user guide 9s12c128dgv1/d v01.05 98 device user guide 9s12c128dgv1/d v01.05 99 b.4 atd characteristics this section describes the characteristics of the analog to digital converter. vrl is not available as a separate pin in the 48 and 52 pin versions. in this case the internal vrl pad is bonded to the vssa pin. the atd is specified and tested for both the 3.3v and 5v range. for ranges between 3.3v and 5v the atd accuracy is generally the same as in the 3.3v range but is not tested in this range in production test. b.4.1 atd operating characteristics in 5v range the table b-3 shows conditions under which the atd operates. the following constraints exist to obtain full-scale, full range results: vssa vrl vin vrh vdda . this constraint exists since the sample buffer amplifier can not drive beyond the power supply levels that it ties to. if the input level goes outside of this range it will effectively be clipped. b.4.2 atd operating characteristics in 3.3v range the table b-3 shows conditions under which the atd operates. the following constraints exist to obtain full-scale, full range results: v ssa v rl v in v rh v dda . this constraint exists since the sample buffer amplifier can not drive table b-3 atd operating characteristics conditions are shown in table a-4 unless otherwise noted. supply voltage 5v-10% <= v dda <=5v+10% num c rating symbol min typ max unit 1d reference potential low high vrl vrh vssa vdda/2 vdda/2 vdda v v 2c differential reference voltage 1 notes : 1. full accuracy is not guaranteed when differential voltage is less than 4.75v vrh-vrl 4.75 5.0 5.25 v 3 d atd clock frequency f atdclk 0.5 2.0 mhz 4d atd 10-bit conversion period clock cycles 2 conv, time at 2.0mhz atd clock f atdclk 2. the minimum time assumes a final sample period of 2 atd clocks cycles while the maximum time assumes a final sample period of 16 atd clocks. n conv10 t conv10 14 7 28 14 cycles m s 5d atd 8-bit conversion period clock cycles 2 conv, time at 2.0mhz atd clock f atdclk n conv10 t conv10 12 6 26 13 cycles m s 5d recovery time (v dda =5.0 volts) t rec 20 m s 6 p reference supply current i ref 0.375 ma device user guide 9s12c128dgv1/d v01.05 100 beyond the power supply levels that it ties to. if the input level goes outside of this range it will effectively be clipped b.4.3 factors influencing accuracy three factors - source resistance, source capacitance and current injection - have an influenceon the accuracy of the atd. b.4.3.1 source resistance: due to the input pin leakage current as specified in table a-6 in conjunction with the source resistance there will be a voltage drop from the signal source to the atd input. the maximum source resistance r s specifies results in an error of less than 1/2 lsb (2.5mv) at the maximum leakage current. if device or operating conditions are less than worst case or leakage-induced error is acceptable, larger values of source resistance is allowable. b.4.3.2 source capacitance when sampling an additional internal capacitor is switched to the input. this can cause a voltage drop due to charge sharing with the external and the pin capacitance. for a maximum sampling error of the input voltage 1lsb, then the external filter capacitor, c f 3 1024 * (c ins - c inn ). table b-4 atd operating characteristics conditions are shown in table a-4 unless otherwise noted; supply voltage 3.3v-10% <= v dda <= 3.3v+10% num c rating symbol min typ max unit 1d reference potential low high v rl v rh v ssa v dda /2 v dda /2 v dda v v 2 c differential reference voltage v rh -v rl 3.0 3.3 3.6 v 3 d atd clock frequency f atdclk 0.5 2.0 mhz 4d atd 10-bit conversion period clock cycles 1 conv, time at 2.0mhz atd clock f atdclk notes : 1. the minimum time assumes a final sample period of 2 atd clocks cycles while the maximum time assumes a final sample period of 16 atd clocks. n conv10 t conv10 14 7 28 14 cycles m s 5d atd 8-bit conversion period clock cycles (1) conv, time at 2.0mhz atd clock f atdclk n conv8 t conv8 12 6 26 13 cycles m s 6d recovery time (v dda =3.3 volts) t rec 20 m s 7 p reference supply current i ref 0.250 ma device user guide 9s12c128dgv1/d v01.05 101 b.4.3.3 current injection there are two cases to consider. 1. a current is injected into the channel being converted. the channel being stressed has conversion values of $3ff ($ff in 8-bit mode) for analog inputs greater than vrh and $000 for values less than vrl unless the current is higher than specified as disruptive conditions. 2. current is injected into pins in the neighborhood of the channel being converted. a portion of this current is picked up by the channel (coupling ratio k), this additional current impacts the accuracy of the conversion depending on the source resistance. the additional input voltage error on the converted channel can be calculated as v err =k*r s * i inj , with i inj being the sum of the currents injected into the two pins adjacent to the converted channel. table b-5 atd electrical characteristics conditions are shown in table a-4 unless otherwise noted num c rating symbol min typ max unit 1 c max input source resistance r s --1k w 2t total input capacitance non sampling sampling c inn c ins 10 15 pf 3 c disruptive analog input current i na -2.5 2.5 ma 4 c coupling ratio positive current injection k p 10 -4 a/a 5 c coupling ratio negative current injection k n 10 -2 a/a device user guide 9s12c128dgv1/d v01.05 102 b.4.4 atd accuracy (5v range) table b-6 specifies the atd conversion performance excluding any errors due to current injection, input capacitance and source resistance. b.4.5 atd accuracy (3.3v range) table b-6 specifies the atd conversion performance excluding any errors due to current injection, input capacitance and source resistance. table b-6 atd conversion performance conditions are shown in table a-4 unless otherwise noted v ref = v rh - v rl = 5.12v. resulting to one 8 bit count = 20mv and one 10 bit count = 5mv f atdclk = 2.0mhz num c rating symbol min typ max unit 1 p 10-bit resolution lsb 5 mv 2 p 10-bit differential nonlinearity dnl C1 1 counts 3 p 10-bit integral nonlinearity inl C2 2 counts 4p 10-bit absolute error 1 notes : 1. these values include quantization error which is inherently 1/2 count for any a/d converter. ae -2.5 2.5 counts 5 p 8-bit resolution lsb 20 mv 6 p 8-bit differential nonlinearity dnl C0.5 0.5 counts 7 p 8-bit integral nonlinearity inl C1.0 0.5 1.0 counts 8p 8-bit absolute error (1) ae -1.5 1 1.5 counts table b-7 atd conversion performance conditions are shown in table a-4 unless otherwise noted v ref = v rh - v rl = 3.328v. resulting to one 8 bit count = 13mv and one 10 bit count = 3.25mv f atdclk = 2.0mhz num c rating symbol min typ max unit 1 p 10-bit resolution lsb 3.25 mv 2 p 10-bit differential nonlinearity dnl C1.5 1.5 counts 3 p 10-bit integral nonlinearity inl C3.5 1.5 3.5 counts 4p 10-bit absolute error 1 notes : 1. these values include the quantization error which is inherently 1/2 count for any a/d converter. ae -5 2.5 5 counts 5 p 8-bit resolution lsb 13 mv 6 p 8-bit differential nonlinearity dnl C0.5 0.5 counts 7 p 8-bit integral nonlinearity inl C1.5 1 1.5 counts 8p 8-bit absolute error (1) ae -2.0 1.5 2.0 counts device user guide 9s12c128dgv1/d v01.05 103 for the following definitions see also figure b-2 . differential non-linearity (dnl) is defined as the difference between two adjacent switching steps. the integral non-linearity (inl) is defined as the sum of all dnls: dnl i () v i v i1 C C 1lsb ------------------------ 1 C = inl n () dnl i () i1 = n ? v n v 0 C 1lsb ------------------- - n C == device user guide 9s12c128dgv1/d v01.05 104 figure b-2 atd accuracy definitions note: figure b-2 shows only definitions, for specification values refer to table b-6 . 1 3.25 vin mv 6.5 9.75 13 16.25 19.5 22.75 26 3305 3309 3312 3315 3318 3321 3324 3328 3292 3295 3299 3302 3289 0 3 2 5 4 7 6 29.25 $3f7 $3f9 $3f8 $3fb $3fa $3fd $3fc $3fe $3ff $3f4 $3f6 $3f5 8 9 1 2 $ff $fe $fd $3f3 10-bit resolution 8-bit resolution ideal transfer curve 10-bit transfer curve 8-bit transfer curve 3286 10-bit absolute error boundary 8-bit absolute error boundary lsb v i-1 v i dnl device user guide 9s12c128dgv1/d v01.05 105 b.5 nvm, flash and eeprom b.5.1 nvm timing the time base for all nvm program or erase operations is derived from the oscillator. a minimum oscillator frequency f nvmosc is required for performing program or erase operations. the nvm modules do not have any means to monitor the frequency and will not prevent program or erase operation at frequencies above or below the specified minimum. attempting to program or erase the nvm modules at a lower frequency a full program or erase transition is not assured. the flash program and erase operations are timed using a clock derived from the oscillator using the fclkdiv and eclkdiv registers respectively. the frequency of this clock must be set within the limits specified as f nvmop . the minimum program and erase times shown in table b-8 are calculated for maximum f nvmop and maximum f bus . the maximum times are calculated for minimum f nvmop and a f bus of 2mhz. b.5.1.1 single word programming the programming time for single word programming is dependant on the bus frequency as a well as on the frequency f nvmop and can be calculated according to the following formula. b.5.1.2 row programming generally the time to program a consecutive word can be calculated as: for the c16, gc16, c32 and gc32 device flash arrays, where up to 32 words in a row can be programmed consecutively by keeping the command pipeline filled, the time to program a whole row is: for the c64, gc64, c96, c128 and gc128 device flash arrays, where up to 64 words in a row can be programmed consecutively by keeping the command pipeline filled, the time to program a whole row is: row programming is more than 2 times faster than single word programming. t swpgm 9 1 f nvmop --------------------- 25 1 f bus ---------- + = t bwpgm 4 1 f nvmop --------------------- 9 1 f bus ---------- + = t brpgm t swpgm 31 t bwpgm + = t brpgm t swpgm 63 t bwpgm + = device user guide 9s12c128dgv1/d v01.05 106 b.5.1.3 sector erase erasing either a 512 byte or 1024 byte flash sector takes: the setup times can be ignored for this operation. b.5.1.4 mass erase erasing a nvm block takes: this is independent of sector size. the setup times can be ignored for this operation. table b-8 nvm timing characteristics conditions are shown in table a-4 unless otherwise noted num c rating symbol min typ max unit 1 d external oscillator clock f nvmosc 0.5 50 1 notes : 1. restrictions for oscillator in crystal mode apply! mhz 2 d bus frequency for programming or erase operations f nvmbus 1 mhz 3 d operating frequency f nvmop 150 200 khz 4 p single word programming time t swpgm 46 2 2. minimum programming times are achieved under maximum nvm operating frequency f nvmop and maximum bus frequen- cy f bus . 74.5 3 3. maximum erase and programming times are achieved under particular combinations of f nvmop and bus frequency f bus . refer to formulae in sections a.3.1.1 - a.3.1.4 for guidance. m s 5 d flash burst programming consecutive word t bwpgm 20.4 2 31 3 m s 6 d flash burst programming time for 32 word row t brpgm 678.4 2 1035.5 3 m s 6 d flash burst programming time for 64 word row t brpgm 1331.2 2 2027.5 3 m s 7 p sector erase time t era 20 4 4. minimum erase times are achieved under maximum nvm operating frequency f nvmop . 26.7 3 ms 8 p mass erase time t mass 100 4 133 3 ms 9 d blank check time flash per block t check 11 5 5. minimum time, if first word in the array is not blank (512 byte sector size). 32778 6 6. maximum time to complete check on an erased block (512 byte sector size) 7 t cyc 7. where t cyc is the system bus clock period. 9 d blank check time flash per block t check 11 8 8. minimum time, if first word in the array is not blank (1024 byte sector size) 65546 9 9. maximum time to complete check on an erased block (1024 byte sector size). 7 t cyc t era 4000 1 f nvmop --------------------- ? t mass 20000 1 f nvmop --------------------- ? device user guide 9s12c128dgv1/d v01.05 107 b.5.2 nvm reliability the reliability of the nvm blocks is guaranteed by stress test during qualification, constant process monitors and burn-in to screen early life failures. the failure rates for data retention and program/erase cycling are specified at < 2ppm defects over lifetime at the operating conditions noted. a program/erase cycle is specified as two transitions of the cell value from erased ? programmed ? erased, 1 ? 0 ? 1. note: all values shown in table b-9 are target values and subject to further extensive characterization. table b-9 nvm reliability characteristics conditions are shown in table a-4 unless otherwise noted num c rating symbol min typ max unit 1c data retention at an average junction temperature of t javg = 85 c t nvmret 15 years 2 c flash number of program/erase cycles n flpe 10,000 cycles device user guide 9s12c128dgv1/d v01.05 108 device user guide 9s12c128dgv1/d v01.05 109 b.6 reset, oscillator and pll this section summarizes the electrical characteristics of the various startup scenarios for oscillator and phase-locked-loop (pll). b.6.1 startup table b-10 summarizes several startup characteristics explained in this section. detailed description of the startup behavior can be found in the clock and reset generator (crg) block user guide. b.6.1.1 por the release level v porr and the assert level v pora are derived from the v dd supply. they are also valid if the device is powered externally. after releasing the por reset the oscillator and the clock quality check are started. if after a time t cqout no valid oscillation is detected, the mcu will start using the internal self clock. the fastest startup time possible is given by n uposc . b.6.1.2 lvr the release level v lvrr and the assert level v lvra are derived from the v dd supply. they are also valid if the device is powered externally. after releasing the lvr reset the oscillator and the clock quality check are started. if after a time t cqout no valid oscillation is detected, the mcu will start using the internal self clock. the fastest startup time possible is given by n uposc . b.6.1.3 sram data retention provided an appropriate external reset signal is applied to the mcu, preventing the cpu from executing code when vdd5 is out of specification limits, the sram contents integrity is guaranteed if after the reset the porf bit in the crg flags register has not been set. table b-10 startup characteristics conditions are shown in table a-4 unless otherwise noted num c rating symbol min typ max unit 1 t por release level v porr 2.07 v 2 t por assert level v pora 0.97 v 3 d reset input pulse width, minimum input time pw rstl 2 t osc 4 d startup from reset n rst 192 196 n osc 5d interrupt pulse width, irq edge-sensitive mode pw irq 20 ns 6 d wait recovery startup time t wrs 14 t cyc device user guide 9s12c128dgv1/d v01.05 110 b.6.1.4 external reset when external reset is asserted for a time greater than pw rstl the crg module generates an internal reset, and the cpu starts fetching the reset vector without doing a clock quality check, if there was an oscillation before reset. b.6.1.5 stop recovery out of stop the controller can be woken up by an external interrupt. a clock quality check as after por is performed before releasing the clocks to the system. b.6.1.6 pseudo stop and wait recovery the recovery from pseudo stop and wait are essentially the same since the oscillator was not stopped in both modes. the controller can be woken up by internal or external interrupts. after t wrs the cpu starts fetching the interrupt vector. b.6.2 oscillator the device features an internal colpitts oscillator. by asserting the xclks input during reset this oscillator can be bypassed allowing the input of a square wave. before asserting the oscillator to the internal system clocks the quality of the oscillation is checked for each start from either power-on, stop or oscillator fail. t cqout specifies the maximum time before switching to the internal self clock mode in case no proper oscillation is detected. the quality monitor also determines the minimum oscillator start-up device user guide 9s12c128dgv1/d v01.05 111 time t uposc . the device features a clock monitor. a time-out is asserted if the frequency of the incoming clock signal is below the clock monitor failureassert frequency f cmfa. b.6.3 phase locked loop the oscillator provides the reference clock for the pll. the plls voltage controlled oscillator (vco) is also the system clock source in self clock mode. b.6.3.1 xfc component selection this section describes the selection of the xfc components to achieve a good filter characteristics. table b-11 oscillator characteristics conditions are shown in table a-4 unless otherwise noted num c rating symbol min typ max unit 1a c crystal oscillator range (colpitts) f osc 0.5 16 mhz 1b c crystal oscillator range (pierce) 1(4) notes : 1. depending on the crystal a damping series resistor might be necessary f osc 0.5 40 mhz 2 p startup current i osc 100 m a 3 c oscillator start-up time (colpitts) t uposc 8 2 2. f osc = 4mhz, c = 22pf. 100 3 3. maximum value is for extreme cases using high q, low frequency crystals ms 4 d clock quality check time-out t cqout 0.45 2.5 s 5 p clock monitor failure assert frequency f cmfa 50 100 200 khz 6p external square wave input frequency 4 4. xclks =0 during reset f ext 0.5 50 mhz 7 d external square wave pulse width low t extl 9.5 ns 8 d external square wave pulse width high t exth 9.5 ns 9 d external square wave rise time t extr 1ns 10 d external square wave fall time t extf 1ns 11 d input capacitance (extal, xtal pins) c in 7pf 12 c dc operating bias in colpitts con?guration on extal pin v dcbias 1.1 v device user guide 9s12c128dgv1/d v01.05 112 figure b-3 basic pll functional diagram the following procedure can be used to calculate the resistance and capacitance values using typical values for k 1 , f 1 and i ch from table b-12. the grey boxes show the calculation for f vco = 50mhz and f ref = 1mhz. e.g., these frequencies are used for f osc = 4mhz and a 25mhz bus clock. the vco gain at the desired vco frequency is approximated by: the phase detector relationship is given by: i ch is the current in tracking mode. the loop bandwidth f c should be chosen to fulfill the gardners stability criteria by at least a factor of 10, typical values are 50. z = 0.9 ensures a good transient response. f osc 1 refdv+1 f ref phase detector vco k v 1 synr+1 f vco loop divider k f 1 2 d f cmp c s r c p vddpll xfc pin k v k 1 e f 1 f vco C () k 1 1v ----------------------- = 100 C e 60 50 C () 100 C ----------------------- - = = -90.48mhz/v k f i ch C k v = = 316.7hz/ w f c 2 z f ref pz 1 z 2 + + ? ?? ------------------------------------------ 1 10 ------ f c f ref 410 -------------- z 0.9 = () ; < ? < f c < 25khz device user guide 9s12c128dgv1/d v01.05 113 and finally the frequency relationship is defined as with the above values the resistance can be calculated. the example is shown for a loop bandwidth f c =10khz: the capacitance c s can now be calculated as: the capacitance c p should be chosen in the range of: b.6.3.2 jitter information the basic functionality of the pll is shown in figure b-3 . with each transition of the clock f cmp , the deviation from the reference clock f ref is measured and input voltage to the vco is adjusted accordingly.the adjustment is done continuously with no abrupt changes in the clock output frequency. noise, voltage, temperature and other factors cause slight variations in the control loop resulting in a clock jitter. this jitter affects the real minimum and maximum clock periods as illustrated in figure b-4 . n f vco f ref ------------- 2 synr 1 + () == = 50 r 2 p nf c k f ---------------------------- - = =2* p *50*10khz/(316.7hz/ w ) =9.9k w =~10k w c s 2 z 2 p f c r --------------------- - 0.516 f c r -------------- - z 0.9 = () ; ? = = 5.19nf =~ 4.7nf c s 20 c p c s 10 c p = 470pf device user guide 9s12c128dgv1/d v01.05 114 figure b-4 jitter definitions the relative deviation of t nom is at its maximum for one clock period, and decreases towards zero for larger number of clock periods (n). defining the jitter as: for n < 100, the following equation is a good fit for the maximum jitter: figure b-5 maximum bus clock jitter approximation 2 3 n-1 n 1 0 t nom t max1 t min1 t maxn t minn jn () max 1 t max n () nt nom --------------------- C 1 t min n () nt nom -------------------- - C , ? ? ?? = j n () j 1 n -------- j 2 + = 1 5 10 20 n j (n) device user guide 9s12c128dgv1/d v01.05 115 this is very important to notice with respect to timers, serial modules where a pre-scaler will eliminate the effect of the jitter to a large extent. table b-12 pll characteristics conditions are shown in table a-4 unless otherwise noted num c rating symbol min typ max unit 1 p self clock mode frequency f scm 1 5.5 mhz 2 d vco locking range f vco 8 50 mhz 3d lock detector transition from acquisition to tracking mode |d trk | 34 % 1 notes : 1. % deviation from target frequency 4 d lock detection |d lock | 0 1.5 % (1) 5 d un-lock detection |d unl | 0.5 2.5 % (1) 6d lock detector transition from tracking to acquisition mode |d unt | 68 % (1) 7c pllon total stabilization delay (auto mode) 2 2. f osc = 4mhz, f bus = 25mhz equivalent f vco = 50mhz: refdv = #$03, synr = #$018, cs = 4.7nf, cp = 470pf, rs = 10k w . t stab 0.5 ms 8d pllon acquisition mode stabilization delay (2) t acq 0.3 ms 9d pllon tracking mode stabilization delay (2) t al 0.2 ms 10 d fitting parameter vco loop gain k 1 -100 mhz/v 11 d fitting parameter vco loop frequency f 1 60 mhz 12 d charge pump current acquisition mode | i ch | 38.5 m a 13 d charge pump current tracking mode | i ch | 3.5 m a 14 c jitter ?t parameter 1 (2) j 1 1.1 % 15 c jitter ?t parameter 2 (2) j 2 0.13 % device user guide 9s12c128dgv1/d v01.05 116 device user guide 9s12c128dgv1/d v01.05 117 b.7 mscan table b-13 mscan wake-up pulse characteristics conditions are shown in table a-4 unless otherwise noted num c rating symbol min typ max 1 p mscan wake-up dominant pulse ?ltered t wup 2 2 p mscan wake-up dominant pulse pass t wup 5 device user guide 9s12c128dgv1/d v01.05 118 device user guide 9s12c128dgv1/d v01.05 119 b.8 spi appendix c electrical specifications this section provides electrical parametrics and ratings for the spi. in table c-1 the measurement conditions are listed. c.1 master mode in figure c-1 the timing diagram for master mode with transmission format cpha=0 is depicted. figure c-1 spi master timing (cpha=0) in figure c-2 the timing diagram for master mode with transmission format cpha=1 is depicted. table c-1 measurement conditions description value unit drive mode full drive mode load capacitance c load, on all outputs 50 pf thresholds for delay measurement points (20% / 80%) vddx v sck (output) sck (output) miso (input) mosi (output) ss 1 (output) 1 9 5 6 msb in 2 bit 6 . . . 1 lsb in msb out 2 lsb out bit 6 . . . 1 11 4 4 2 10 (cpol = 0) (cpol = 1) 3 13 13 1.if configured as an output. 2. lsbf = 0. for lsbf = 1, bit order is lsb, bit 1, ..., bit 6, msb. 12 12 device user guide 9s12c128dgv1/d v01.05 120 figure c-2 spi master timing (cpha=1) in table c-2 the timing characteristics for master mode are listed. table c-2 spi master mode timing characteristics num c characteristic symbol unit min typ max 1 p sck frequency f sck 1/2048 1 / 2 f bus 1 p sck period t sck 2 2048 t bus 2 d enable lead time t lead 1/2 t sck 3 d enable lag time t lag 1/2 t sck 4 d clock (sck) high or low time t wsck 1/2 t sck 5 d data setup time (inputs) t su 8 ns 6 d data hold time (inputs) t hi 8 ns 9 d data valid after sck edge t vsck 30 ns 10 d data valid after ss fall (cpha=0) t vss 15 ns 11 d data hold time (outputs) t ho 20 ns 12 d rise and fall time inputs t r? 8 ns 13 d rise and fall time outputs t rfo 8 ns sck (output) sck (output) miso (input) mosi (output) 1 5 6 msb in 2 bit 6 . . . 1 lsb in master msb out 2 master lsb out bit 6 . . . 1 4 4 9 12 13 11 port data (cpol = 0) (cpol = 1) port data ss 1 (output) 2 12 13 3 1.if configured as output 2. lsbf = 0. for lsbf = 1, bit order is lsb, bit 1, ..., bit 6, msb. device user guide 9s12c128dgv1/d v01.05 121 c.2 slave mode in figure c-3 the timing diagram for slave mode with transmission format cpha=0 is depicted. figure c-3 spi slave timing (cpha=0) in figure c-4 the timing diagram for slave mode with transmission format cpha=1 is depicted. sck (input) sck (input) mosi (input) miso (output) ss (input) 1 9 5 6 msb in bit 6 . . . 1 lsb in slave msb slave lsb out bit 6 . . . 1 11 4 4 2 7 (cpol = 0) (cpol = 1) 3 13 note: not defined! 12 12 11 see 13 note 8 10 see note device user guide 9s12c128dgv1/d v01.05 122 figure c-4 spi slave timing (cpha=1) in table c-3 the timing characteristics for slave mode are listed. table c-3 spi slave mode timing characteristics num c characteristic symbol unit min typ max 1 d sck frequency f sck dc 1 / 4 f bus 1 p sck period t sck 4 t bus 2 d enable lead time t lead 4 t bus 3 d enable lag time t lag 4 t bus 4 d clock (sck) high or low time t wsck 4 t bus 5 d data setup time (inputs) t su 8 ns 6 d data hold time (inputs) t hi 8 ns 7d slave access time (time to data active) t a 20 ns 8 d slave miso disable time t dis 22 ns 9 d data valid after sck edge t vsck 30 + t bus 1 notes : 1. t bus added due to internal synchronization delay ns 10 d data valid after ss fall t vss 30 + t bus 1 ns 11 d data hold time (outputs) t ho 20 ns 12 d rise and fall time inputs t r? 8 ns 13 d rise and fall time outputs t rfo 8 ns sck (input) sck (input) mosi (input) miso (output) 1 5 6 msb in bit 6 . . . 1 lsb in msb out slave lsb out bit 6 . . . 1 4 4 9 12 13 11 (cpol = 0) (cpol = 1) ss (input) 2 12 13 3 note: not defined! slave 7 8 see note device user guide 9s12c128dgv1/d v01.05 123 c.3 external bus timing a timing diagram of the external multiplexed-bus is illustrated in figure c-5 with the actual timing values shown on table table c-4. all major bus signals are included in the diagram. while both a data write and data read cycle are shown, only one or the other would occur on a particular bus cycle. c.3.1 general muxed bus timing the expanded bus timings are highly dependent on the load conditions. the timing parameters shown assume a balanced load across all outputs. figure c-5 general external bus timing addr/data (read) addr/data (write) addr data data 5 10 11 8 16 6 eclk 1, 2 3 4 addr data data 12 15 9 7 14 13 lstrb 22 no a cc 25 pipo0 pipo1, pe6,5 28 20 21 23 26 29 24 27 r/ w 17 19 18 pe4 pa, pb pa, pb pe2 pe3 pe7 device user guide 9s12c128dgv1/d v01.05 124 table c-4 expanded bus timing characteristics (5v range) conditions are 4.75v < vddx < 5.25v, junction temperature -40?c to +140?c, c load = 50pf num c rating symbol min typ max unit 1 p frequency of operation (e-clock) f o 0 25.0 mhz 2 p cycle time t cyc 40 ns 3 d pulse width, e low pw el 19 ns 4d pulse width, e high 1 pw eh 19 ns 5 d address delay time t ad 8ns 6d address valid time to e rise (pw el Ct ad )t av 11 ns 7 d muxed address hold time t mah 2ns 8 d address hold to data valid t ahds 7ns 9 d data hold to address t dha 2ns 10 d read data setup time t dsr 13 ns 11 d read data hold time t dhr 0ns 12 d write data delay time t ddw 7ns 13 d write data hold time t dhw 2ns 14 d write data setup time (1) (pw eh Ct ddw ) t dsw 12 ns 15 d address access time (1) (t cyc Ct ad Ct dsr ) t acca 19 ns 16 d e high access time (1) (pw eh Ct dsr ) t acce 6ns 17 d read/write delay time t rwd 7ns 18 d read/write valid time to e rise (pw el Ct rwd )t rwv 14 ns 19 d read/write hold time t rwh 2ns 20 d low strobe delay time t lsd 7ns 21 d low strobe valid time to e rise (pw el Ct lsd )t lsv 14 ns 22 d low strobe hold time t lsh 2ns 23 d noacc strobe delay time t nod 7ns 24 d noacc valid time to e rise (pw el Ct lsd )t nov 14 ns 25 d noacc hold time t noh 2ns 26 d ipipo[1:0] delay time t p0d 27ns 27 d ipipo[1:0] valid time to e rise (pw el Ct p0d )t p0v 11 ns 28 d ipipo[1:0] delay time (1) (pw eh -t p1v ) t p1d 225ns 29 d ipipo[1:0] valid time to e fall t p1v 11 ns notes : 1. affected by clock stretch: add n x t cyc where n=0,1,2 or 3, depending on the number of clock stretches. device user guide 9s12c128dgv1/d v01.05 125 table c-5 expanded bus timing characteristics (3.3v range) conditions are vddx=3.3v+/-10%, junction temperature -40?c to +140?c, c load = 50pf num c rating symbol min typ max unit 1 d frequency of operation (e-clock) f o 0 16.0 mhz 2 d cycle time t cyc 62.5 ns 3 d pulse width, e low pw el 30 ns 4d pulse width, e high 1 pw eh 30 ns 5 d address delay time t ad 16 ns 6d address valid time to e rise (pw el Ct ad )t av 16 ns 7 d muxed address hold time t mah 2ns 8 d address hold to data valid t ahds 7ns 9 d data hold to address t dha 2ns 10 d read data setup time t dsr 15 ns 11 d read data hold time t dhr 0ns 12 d write data delay time t ddw 15 ns 13 d write data hold time t dhw 2ns 14 d write data setup time (1) (pw eh Ct ddw ) t dsw 15 ns 15 d address access time (1) t acca 29 ns 16 d e high access time (1) (pw eh Ct dsr ) t acce 15 ns 17 d read/write delay time t rwd 14 ns 18 d read/write valid time to e rise (pw el Ct rwd )t rwv 16 ns 19 d read/write hold time t rwh 2ns 20 d low strobe delay time t lsd 14 ns 21 d low strobe valid time to e rise (pw el Ct lsd )t lsv 16 ns 22 d low strobe hold time t lsh 2ns 23 d noacc strobe delay time t nod 14 ns 24 d noacc valid time to e rise (pw el Ct lsd )t nov 16 ns 25 d noacc hold time t noh 2ns 26 d ipipo[1:0] delay time t p0d 214ns 27 d ipipo[1:0] valid time to e rise (pw el Ct p0d )t p0v 16 ns 28 d ipipo[1:0] delay time (1) t p1d 225ns 29 d ipipo[1:0] valid time to e fall t p1v 11 ns notes : 1. affected by clock stretch: add n x t cyc where n=0,1,2 or 3, depending on the number of clock stretches. device user guide 9s12c128dgv1/d v01.05 126 device user guide 9s12c128dgv1/d v01.05 127 appendix d package information d.1 general this section provides the physical dimensions of the mc9s12c family and mc9s12gc family packages 48lqfp, 52lqfp, 80qfp. device user guide 9s12c128dgv1/d v01.05 128 d.2 80-pin qfp package figure d-1 80-pin qfp mechanical dimensions (case no. 841b) notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. datum plane -h- is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. 4. datums -a-, -b- and -d- to be determined at datum plane -h-. 5. dimensions s and v to be determined at seating plane -c-. 6. dimensions a and b do not include mold protrusion. allowable protrusion is 0.25 per side. dimensions a and b do include mold mismatch and are determined at datum plane -h-. 7. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.08 total in excess of the d dimension at maximum material condition. dambar cannot be located on the lower radius or the foot. section b-b 61 60 detail a l 41 40 80 -a- l -d- a s a-b m 0.20 d s h 0.05 a-b s 120 21 -b- b v j f n d view rotated 90 detail a b b p -a-,-b-,-d- e h g m m detail c seating plane -c- c datum plane 0.10 -h- datum plane -h- u t r q k w x detail c dim min max millimeters a 13.90 14.10 b 13.90 14.10 c 2.15 2.45 d 0.22 0.38 e 2.00 2.40 f 0.22 0.33 g 0.65 bsc h --- 0.25 j 0.13 0.23 k 0.65 0.95 l 12.35 ref m 510 n 0.13 0.17 p 0.325 bsc q 07 r 0.13 0.30 s 16.95 17.45 t 0.13 --- u 0 --- v 16.95 17.45 w 0.35 0.45 x 1.6 ref s a-b m 0.20 d s c s a-b m 0.20 d s h 0.05 d s a-b m 0.20 d s c s a-b m 0.20 d s c device user guide 9s12c128dgv1/d v01.05 129 d.3 52-pin lqfp package figure d-2 52-pin lqfp mechanical dimensions (case no. 848d-03) f notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter 3. datum plane -h- is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. 4. datums -l-, -m- and -n- to be determined at datum plane -h-. 5. dimensions s and v to be determined at seating plane -t-. 6. dimensions a and b do not include mold protrusion. allowable protrusion is 0.25 (0.010) per side. dimensions a and b do include mold mismatch and are determined at datum plane -h- 7. dimension d does not include dambar protrusion. dambar protrusion shall not cause the lead width to exceed 0.46 (0.018). minimum space between protrusion and adjacent lead or protrusion 0.07 (0.003). view aa ab ab view y section ab-ab rotated 90 clockwise dim a min max min max inches 10.00 bsc 0.394 bsc millimeters a1 5.00 bsc 0.197 bsc b 10.00 bsc 0.394 bsc b1 5.00 bsc 0.197 bsc c --- 1.70 --- 0.067 c1 0.05 0.20 0.002 0.008 c2 1.30 1.50 0.051 0.059 d 0.20 0.40 0.008 0.016 e 0.45 0.030 f 0.22 0.35 0.009 0.014 g 0.65 bsc 0.75 0.018 0.026 bsc j 0.07 0.20 0.003 0.008 k 0.50 ref 0.020 ref r1 0.08 0.20 0.003 0.008 s 12.00 bsc 0.472 bsc s1 6.00 bsc 0.236 bsc u 0.09 0.16 0.004 0.006 v 12.00 bsc 0.472 bsc v1 6.00 bsc 0.236 bsc w 0.20 ref 0.008 ref z 1.00 ref 0.039 ref c l -x- x=l, m, n 1 13 14 26 27 39 40 52 4x 13 tips 4x n 0.20 (0.008) h l-m n 0.20 (0.008) t l-m seating plane c 0.10 (0.004) t 4x q 3 4x q 2 s 0.05 (0.002) 0.25 (0.010) gage plane c2 c1 w k e z s l-m m 0.13 (0.005) n s t plating base metal d j u b v b1 a s v1 a1 s1 -l- -n- -m- -h- -t- q 1 q g q 1 q q 3 q 2 07 12 07 0 0 --- --- ref 12 ref 3x view y view aa 2x r r1 12 ref 12 ref device user guide 9s12c128dgv1/d v01.05 130 d.4 48-pin lqfp package figure d-3 48-pin lqfp mechanical dimensions (case no.932-03 issue f) a a1 z 0.200 ab t-u 4x z 0.200 ac t-u 4x b b1 1 12 13 24 25 36 37 48 s1 s v v1 p ae ae t, u, z detail y detail y base metal n j f d t-u m 0.080 z ac section ae-ae ad g 0.080 ac m top & bottom l w k aa e c h 0.250 r 9 detail ad notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 1. controlling dimension: millimeter. 2. datum plane ab is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. 3. datums t, u, and z to be determined at datum plane ab. 4. dimensions s and v to be determined at seating plane ac. 5. dimensions a and b do not include mold protrusion. allowable protrusion is 0.250 per side. dimensions a and b do include mold mismatch and are determined at datum plane ab. 6. dimension d does not include dambar protrusion. dambar protrusion shall not cause the d dimension to exceed 0.350. 7. minimum solder plate thickness shall be 0.0076. 8. exact shape of each corner is optional. t u z ab ac gauge plane dim a min max 7.000 bsc millimeters a1 3.500 bsc b 7.000 bsc b1 3.500 bsc c 1.400 1.600 d 0.170 0.270 e 1.350 1.450 f 0.170 0.230 g 0.500 bsc h 0.050 0.150 j 0.090 0.200 k 0.500 0.700 m 12 ref n 0.090 0.160 p 0.250 bsc l 07 r 0.150 0.250 s 9.000 bsc s1 4.500 bsc v 9.000 bsc v1 4.500 bsc w 0.200 ref aa 1.000 ref device user guide 9s12c128dgv1/d v01.05 131 appendix e emulation information e.1 general in order to emulate the mc9s12c and 9s12gc-family devices, external addressing of a 128k memory map is required. this is provided in a 112 lqfp package version which includes the 3 necessary extra external address bus signals via portk. this package version is for emulation only and not provided as a general production package. figure 19-1 pin assignments in 112-pin lqfp vrh vdda nc pad07/an07 nc pad06/an06 nc pad05/an05 nc pad04/an04 nc pad03/an03 nc pad02/an02 nc pad01/an01 nc pad00/an00 vss2 vdd2 pa7/addr15/data15 pa6/addr14/data14 pa5/addr13/data13 pa4/addr12/data12 pa3/addr11/data11 pa2/addr10/data10 pa1/addr9/data9 pa0/addr8/data8 pp4/kwp4/pw4 pp5/kpw5/pwm nc pp7/kwp7/pw7 nc vddx vssx pm0/rxcan pm1/txcan pm2/mis pm3/ ss pm4/mosi pm5/sck pj6/kwj6 pj7/kwj7 nc nc pp6/kwp6/romone nc nc ps3 ps2 ps1/txd ps0/rxd nc nc vssa vrl pw3/kwp3/pp3 pw2/kwp2/pp2 pw1/kwp1/pp1 /pw0/kwp0/pp0 nc xaddr16/pk2 xaddr15/pk1 xaddr14/pk0 ioc0/pt0 ioc1/pt1 ioc2/pt2 ioc3/pt3 vdd1 vss1 ioc4/pt4 ioc5/pt5 ioc6/pt6 ioc7/pt7 nc nc nc nc modc/ t a ghi/bkgd addr0/data0/pb0 addr1/data1/pb1 addr2/data2/pb2 addr3/data3/pb3 addr4/data4/pb4 addr5/data5/pb5 addr6/data6/pb6 addr7/data7/pb7 nc nc nc nc xclks/noacc/pe7 modb/ipipe1/pe6 moda/ipipe0/pe5 eclk/pe4 vssr vddr reset vddpll xfc vsspll extal xtal test nc nc nc nc lstrb/ t a glo/pe3 r/ w/pe2 irq/pe1 xirq/pe0 signals shown in bold are available only in the 112 pin package. pins marked "nc" are not connected mc9s12c family mc9s12gc family 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 device user guide 9s12c128dgv1/d v01.05 132 e.1.1 pk[2:0] / xaddr[16:14] pk2-pk0 provide the expanded address xaddr[16:14] for the external bus. refer to the s12 core user guide for detailed information about external address page access. the reset state of ddrk in the s12_core is $00, configuring the pins as inputs. the reset state of pupke in the pucr register of the s12_core is "1" enabling the internal pullup resistors at portk[2:0]. in this reset state the pull-up resistors provide a defined state and prevent a floating input, thereby preventing unneccesary current consumption at the input stage. pin name function 1 pin name function 2 power domain internal pull resistor description ctrl reset state pk[2:0] xaddr[16:14] vddx pupke up port k i/o pins device user guide 9s12c128dgv1/d v01.05 133 e.2 112-pin lqfp package figure 19-2 112-pin lqfp mechanical dimensions (case no. 987)80-pin qfp mechanical dimensions (case no. 841b) dim a min max 20.000 bsc millimeters a1 10.000 bsc b 20.000 bsc b1 10.000 bsc c --- 1.600 c1 0.050 0.150 c2 1.350 1.450 d 0.270 0.370 e 0.450 0.750 f 0.270 0.330 g 0.650 bsc j 0.090 0.170 k 0.500 ref p 0.325 bsc r1 0.100 0.200 r2 0.100 0.200 s 22.000 bsc s1 11.000 bsc v 22.000 bsc v1 11.000 bsc y 0.250 ref z 1.000 ref aa 0.090 0.160 q q q q 11 11 13 7 13 view y l-m 0.20 n t 4x 4x 28 tips pin 1 ident 1 112 85 84 28 57 29 56 b v v1 b1 a1 s1 a s view ab 0.10 3 c c2 q 2 q 0.050 seating plane gage plane 1 q q view ab c1 (z) (y) e (k) r2 r1 0.25 j1 view y j1 p g 108x 4x section j1-j1 base rotated 90 counterclockwise metal j aa f d l-m m 0.13 n t 1 2 3 c l l-m 0.20 n t l n m t t 112x x x=l, m or n r r notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. dimensions in millimeters. 3. datums l, m and n to be determined at seating plane, datum t. 4. dimensions s and v to be determined at seating plane, datum t. 5. dimensions a and b do not include mold protrusion. allowable protrusion is 0.25 per side. dimensions a and b include mold mismatch. 6. dimension d does not include dambar protrusion. allowable dambar protrusion shall not cause the d dimension to exceed 0.46. 8 3 0 device user guide 9s12c128dgv1/d v01.05 134 device user guide 9s12c128dgv1/d v01.05 135 device user guide end sheet device user guide 9s12c128dgv1/d v01.05 136 final page of 136 pages |
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